The workshops this year offer a wide range of topics addressing the concerns of the novice ASIC designer (schematic based design with gate level simulation) as well as the experienced ASIC designer (text based design with behavioral simulation). Included are several workshops directed at specific types of ASIC designs and their applications.
The workshops are primarily targeted towards ASIC designers and systems engineers. The aim is to provide the individual with hands on experience oriented towards practical usefulness and application. The workshops are offered over two days with an attempt at scheduling in such a way that the Day Two workshops are a natural follow on to the Day One workshops taking into consideration each individual's various experience level and needs.
Day One finds the workshop "Introduction to VLSI and ASIC Design Tools" by Rochester Institute of Technology a natural precursor to the Day Two workshops "Testing Digital Circuits and Designing Scan and Self-test" by University of Texas / IBM Corporation and "Topdown Design with VHDL" by Viewlogic Systems Incorporated.
Day One is rounded out with Altera Corporation's "Digital Design with VHDL" workshop and the analysis of VHDL via workshops by Synopsys Incorporated "An Excursion into VHDL" and "Experimenting with VHDL".
For the experienced ASIC designer choosing to address particular design issues, Day Two workshops "Designing a Rambus ASIC" by Rambus Incorporated, "Ensuring Correct Timing in a High Performance Gate Array" by California Institute of Technology and "Architectural Exploration with Mistral2" by Rochester Institute of "Technology / Mentor Graphics Corporation represent three workshops worth of practical ASIC design and application.
All workshops provide the student with handouts and other related material and most are hands-on (PC or workstation) and presented in a lab environment at a local university with transportation to and from the convention site provided.
This workshop is designed to give the beginning ASIC designers or project managers an introduction to the electronic design automation (EDA) tools, including schematic capture, VHDL capture, FPGA simulation and digital circuit simulation. HP workstations Mentor Graphics' EDA tools, including design architect, quicksim II, quick VHDL, Auto Logic or Synopsys synthesis tools will be used.
The IEEE-1076 standard hardware description language, VHDL, is rapidly becoming a prominent component of the design, documentation, and simulation environment of the electronics industry. This workshop presents an innovative series of tightly coupled VHDL models that will introduce many of the fundamental principles of VHDL.
This workshop explores a set of experiments that both challenge and reinforce the participant's understanding of how the various VHDL constructs behave and interact with each other. Each experiment is self contained and isolates key design issues and caveats based on real- world VHDL coding scenarios.
The goal of this workshop is to introduce the non-VHDL user to the basic concepts of writing synthesizable VHDL descriptions of digital designs. Attendees will begin learning with simple logical descriptions and quickly move towards more useful constructs, such as counters and state machines. The workshop emphasizes a hands-on approach, with roughly fifty percent of the time spent writing VHDL and working with a VHDL synthesis tool. The VHDL synthesis tool that will be used in this workshop is Altera Corporation's MAX+PLUS II, although the concepts of synthesizable VHDL are independent of the synthesis tool, and can be applied to the creation of any VHDL design description.
The focus of this workshop is the testing of digital circuits and those design methods which make testing a simpler task. As logic circuits become larger, faster, and more complex, as boards become more difficult to physically access, and as systems become more difficult to diagnose, the costs associated with testing continue to increase. This workshop will provide practical methods for keeping testing costs at a reasonable level while still providing acceptable confidence in the viability of the units passing the testing process.
This workshop covers the fundamental elements of Rambus technology - a revolutionary new type of memory interconnect which transfers data at 500 MB/s. Attendees will gain a thorough understanding of Rambus memory technology and will be able to design an ASIC memory controller optimized for the Rambus architecture using the Rambus ASIC interface macro cell (RAC). Documentation and design examples will be provided, along with a description of Toshiba's ASIC design flow incorporating the RAC macro cell.
The workshop will explain the various methods for meeting the timing requirements of a design using sub-micron CMOS or GaAs gate arrays, without iterating on Place-and-Route. Modern techniques such as Intelligent Front Annotation and Hierarchical Floor-planning will be discussed. The workshop is not vendor specific. Workshop notes will be provided.
The workshop will concentrate on the specification, simulation and implementation of Digital Signal Processing (DSP) systems with Mentor Graphics DSP Station. The full range of commercial DSP processor solutions to ASIC implementations will be covered. Hands-on experience is possible with two examples describing a simple and a more complex system. Workshop handouts and example descriptions will be provided.
The workshop will demonstrate how to effectively use VHDL to get the best synthesis results. Starting with a VHDL behavioral abstraction of a design, the workshop will introduce architectural synthesis and VHDL simulation as a approach to quickly and effectively explore performance tradeoffs associated with different architectural implementations. The design will then continue through the synthesis process, where we will explore the various types of control you have over the gate level synthesis process, including timing optimization, and tradeoffs between speed and area optimization.