EDUCATIONAL TUTORIALS
David M. Boisvert, Chair
East Coast Labs, Inc.
The ASIC Conference will hold 12 tutorial sessions, scheduled
throughout the conference. They are designed to educate attendees
and complement the paper presentations.
Thursday ______________________Session 5
8:30 a.m. VHDL-A: Analog Extension to VHDL
(T1) Richard Shi
60 min. Analogy Inc., Beavertown, OR
Thursday _____________________Session 6a
8:30 a.m. Experiences in Teaching ASIC Design Using
Xilinx FPGA and Mentor Graphics Tools
(T2) Shih-Lien Lu
20 min. Oregon State University, Corvallis, OR
Thursday _____________________Session 6c
1:30 p.m. Tutorial: FPGA Development Tools: Keeping
Pace with Design Complexity
(T6-2) Bradley K. Fawcett
20 min. Xilinx Inc. San Jose, CA
Thursday _____________________Session 8
1:50 p.m. A Digital CMOS Programmable Clock Generator
(T4) P.T. Holler
20 min. AT&T Bell Labs, Allentown, PA
Thursday _____________________Session 9
1:50 p.m. Recent Development in Simulation
(T5) Albert Davis
60 min. Rochester Institute of Technology, Rochester, NY
2:50 p.m. Behavioral Modeling for Top Down Mixed Signal Design
(T6) Prasad Subramaniam
40 min. AT&T Design Automation, Murray Hill, NJ
Thursday _____________________Session 10
2:40 p.m. Package and Test Techniques for Known Good ASIC Die
(T7) Richard Chrusciel
40 min. ETEC Inc., Peabody, MA
Thursday _____________________Session 12
2:55 p.m. PREP Benchmarks Reveal Performance and
Capacity Tradeoffs of Programmable Logic Devices
(T8) Stephen Kliman
40 min. Altera Corp., San Jose, CA
3:35 p.m. Synchronous Performance and Reliability
Improvement in Pipelined ASICs
(T9) Eby Friedman
60 min. University of Rochester, NY
Friday ----------------------Session 13
8:30 a.m. Implementing a SCMOS Boundary-Scan Architecture
(T10) Bibiche Geuskens
40 min. Rensselaer Polytechnic Institute, Troy, NY
9:10 a.m. On Choosing the Right Error Models for Circuit Testing
(T11) Ting-Ting Lin
40 min. University of California at San Diego
Friday _______________________Session 14
8:30 a.m. Personal Appliance System and ASIC Architecture
(T12) Robert T. Franzo
90 min. AT&T Bell Labs