Bryan D. Ackland, AT&T Bell LabsWednesday 10:15 - 11:45 a.m.
Bryan D. Ackland, AT&T Bell LabsEmerging multimedia applications based on video signal processing require processing in the range of 100 - 10IX MIPS supplied by silicon costing less than $100. This combination of price and performance would argue for a full custom dedicated architecture. The pace at which the marketplace is changing, however, combined with the variety of new products and services being proposed calls for programmable architectures in which a common hardware platform can be used to rapidly bring new products to market based on software development only. This talk will discuss architectural options that seek to satisfy these opposing forces. Included will be a discussion of some of the key algorithmic operations required by current video coding standards. Tradeoffs between cost, performance, programmability and design cycle will be examined. Software only solutions will also be discussed. Examples of commercial architectures will be used to highlight the strengths and weaknesses of these various approaches along with a more detailed description of an AT&T chip set.
Martin Mallinson, Crimble Micro Test
Beginning with the representation of analog signals we will discuss the various techniques to convert between analog and digital signals. The talk will cover basic principles with special emphasis on practical problems. Wherever possible we will use an existing design and show how the designer tacKled the practical problems in implementation. Our intuition will take us through most issues - we can understand how a voltage divider works for example. Some systems require us to trust the mathematical representation - we will take the time to understand how error correction can work and why sigma delta converters are olten the best solution to a data acquisition problem. VLSI analog parts can build ADCs in new ways - it is becoming practical to use one analog block for every level in a 12 bit converter - we conclude with some examples of these circuits.
Lou Scheffer, Cadence Design Systems, Inc.
Progress in ASICs and progress in CAD are closely interdependent, and three new developments are currently driving the evolution of ASIC CAD. The first two are traditional: the physical effects of newer, smaller processes, and the complexity issues arising from rapidly increasing gate counts. The physical effects at the deep sub-micron level are well understood, and should not be a limiting factor in ASIC development. Complexity issues are more of a problem - designing a large ASIC is now very similar to developing a large piece of software. Designers will handle this by a combination of techniques borrowed from software engineering, and new techniques such as emulation. One new concern is that we can now build ASICs so large that error free design cannot be expected, even with the best known practices. New techniques such as formal verification will help, but not solve the problem. The remaining errors must be considered by system level tools. The third development in the ASIC world, and the main focus of this talk, is the use of ASICs in new applications such as wireless, portable and high-speed telecommunication. Traditional ASIC design techniques - HDL entry, logic simulation, synthesis, placement, and routing - will not be enough to serve these markets. At the architecture level, the design of such chips must consider queuing theory, signal to noise ratios, error recovery strategies, availability requirements, and other 'high level' system specifications. At the circuit level, ASIC CAD tools must handle mixed RF and digital circuits, power consumption minimization, and high speed analog as well as the digital logic. This talk covers the tools and methodologies required to take full advantage of ASICs in such environments.