Technical Sessions

SESSION 1: Analog & Mixed Signal

Session Summary -- Jeff Everts, Chair

A Mixed-Signal ASIC for Piston Temperature Measurement in Internal Combustion Engines -- Eric G. Chowanietz
An Electro-Optical Standard-Cell for ASIC Design -- Sihin Seyfou and Richard J. Auletta
A Word/Bit Parallel Inexact Match Content Addressable Memory -- W. Robert Daasch and Jack Lee
A 1-MHz and 16-bit "sigma""delta" DAC With a 224th-Order Reconstruction FIR-Filter Using Only 9 Nonzero Taps -- Christer Jansson and Christer Svensson
A Dual-Channel Analog Servo-Signal Processor for 13GB Tape Drives -- Sriram Narayan and Hans W. Klein
An Analog VLSI Neural Network for Real-Time Image Processing in Industrial Applications -- M. Valle, M. Onorato, F. Oddone, G.M. Bisio, DD. Caviglia
Multi-GHz CMOS Oscillators -- Thad Gabara, W.Fischer
A CMOS Low Voltage High Performance Interface -- J.D. Trotter, S. Rekhi, V. Chava, and P.C. Kale
Constant Delay Logic Technology -- David W. Hall, J.G. Dooley, and A. Hernandez

SESSION 2: Synthesis

Session Summary -- Scott Baker, Chair

Combining the Top-Down Approach with Bottom-Up Advantages in Logic Synthesis -- Volker Keifer
Scheduling in the Presence of Conditional Constructs and the Optimization of Control Structures -- Jon Ainscough
Structure Exploration in High-Level Language Description for Logic Synthesis Yulin Chen
Exploring ASIC Design Space at the System Level with a Neural Network Estimator -- Peter Ellervee
Synthesis of Memories from Behavioral HDLs -- Nels Vander Zanden
High Level Synthesis in DSP ASIC Optimization -- Jouni Isoaho
A Microprocessor in Four-Month Development of the FHOP -- Thomas Gieringer

SESSION 3: Circuits & Architecture

Session Summary -- Ramalingam Sridhar, Chair

A Pass Transistor Regulator Structure for Implementing Multi-Level Combinational Circuits -- Jose Luis Neves and A. Albicki
CMOS Wave Pipelining using Transmission-Gate Logic -- Xuguang Zhang and R. Sridhar
Tapered Buffers for Gate Array and Standard Cell Circuits -- Brian S. Cherkauer and E. Friedman
Low Power via Reduced Switching Activity and its Application to PLAs
-- Razak Hossain and A. Albicki
Quasi-Static CMOS -- Thad Gabara
A Static Technique for High-Speed CMOS State Machine Design -- Kevin McLaughlin, A. Schwab and J. Aylor
A 200ps 0.5micron CMOS GAte Array Family with High-Speed Modules -- Yoji Nishio, H. Hara, M. Iwamura, Y. Kaminaga, K.Koike, K. Hirose, T. Noto, Y. Yamamoto and T. Ono
A Mixed Asymmetric/Symmetric (MASS) MOSFET Cell for ASICs -- Kouichi Kumagai, S.Kurosawa, H. Iwaki, N. Hamatake, A. Yoshino, K. Okumura, K. Ohuchi, K.Nakajima, A. Asahina and Y. Yamazaki

SESSION 4A: Physical Design

Session Summary -- Mike Smith, Chair

Datapath Cell Design Strategy for Channelless Routing -- Naresh Kumar Sehgal, C. Y. Chen, and J. Acken
Synthesizing Distributed Buffer Clock Trees for High Performance ASICs -- Jose Luis Neves and E. Friedman
Optimal Buffered Clock Tree Synthesis -- Jae Chung and C.K. Cheng
An Efficient Routing Technique to Resolve the Current-Crowding Effect in the Power Grid Structure of Gate Arrays -- Chingchi Yao, I. Yamamoto, and S.Nomura
High-Performance Routing for Field-Programmable Gate Arrays -- Michael J. Alexander and G. Robins

SESSION 4B: Design Capture and Partitioning

Session Summary -- Gabriel Robins, Chair

Computer-Aided Design-Verification Vector Generation -- M. Nance Ericson and C. Stroud
Graphical Specification of Digital Systems Using Interval Temporal Logic -- M. G. Hadjinicolaou, R. B. Hughes, and G. Musgrave
Simple Yet Effective Replication for FPGA Partitioning -- Dinesh Bhatia and V. Narasimhan
Hardware/Software Codesign for Digital Communication Processing -- Hakim Saheb and M. Dang

SESSION 5: Hardware Description Languages

Session Summary -- George Brown, Chair

VHDL-A: Analog Extension to VHDL -- Richard Shi, E. Christen, P. Liebmann, S. Krolikoski, and W. Zhou
AHDL Modeling to Support Top-down Design of Mixed-signal ASICs -- J.A. Barby, S.E. Rehan, and M.I. Elmasry
Hierarchical Mixed-level Simulation of VHDL Descriptions -- Tanay Karnik, D. G. Saab, S.M. Kang, Y.K. Lee, K.H. Kim
Macromodeling CMOS Circuits for Event Driven Simulation -- J. Donald Trotter, S. Saripella, D.L. Ledlow, N. Pidugu, D. Kapoor
FSM Synthesis on FPGA Architectures -- L. Burgun, N. Dictus, A. Greiner, E. Prado, C. Sarwary
Performance-Driven Technology Mapping for LUT-Based FPGAs -- Hyunchul Shin, C. Kim, and Y. Yu
A Systematic Approach in Designing a Complex System with VHDL -- Donald L. Hung

SESSION 6A: ASIC Education

Session Summary -- Cherrice Traver, Chair

Education in ASIC Design Using the SET Concept -- K. Hein & A. Rucinski
Using HYPER to Teach Datapath Design Techniques in an ASIC Design Course -- Bob Reese
A Structure of Modern VLSI Curriculum -- A. Hemani, M. Mokthari, J. Isoaho,H. Tenhunen
A Proposed Training Curriculum in ASIC Design -- M. Mark Farhoomand

SESSION 6B: ASIC Design Methods

Session Summary -- Cherrice Traver, Chair

A First Pass ASIC Development Methodology Using Logic Emulation -- Thomas Chan, B. Yeh, and Eileen Hu
Rapid Prototyping of a Cellular Processor -- Vanya Amla and R. Auletta
Designing High Complexity ASIC using the Alliance CAD System -- A. Greiner, L. Lucas, and F. Wajsburt
Taking Advantage of Reconfigurable Logic -- Bradly K. Fawcett

SESSION 6C: Management & Economics

Session Summary -- Mely Chen-Chi, Chair

FPGA Development Tools: Keeping Pace with Design Complexity -- Bradley K. Fawcett
A Methodology for Design Verification -- Eileen Hu, B.Yeh, and T. Chan
Adoption & Utilization of ASIC Technologies in European SMI's -- Tarja Juhola, H. Tenhunen, and I. Nielsen

SESSION 7: DSP and Imaging

Session Summary -- Mark Schrader, Chair

A Fast Reed-Solomon and Cyclic Redundancy Check Encoding Algorithm for Optical Disk Error Control -- Rom-Shen Kao and V. Gibbs
A VLSI Design for Full-Search Block Matching Motion Estimation -- Seung Hyun Nam
Implementing a Digital Signal Processor for an Electronic Still Camera Using Multiple--FPGA's -- Sin-shuh Wang and T.C. Chung
A Flexible Repetitive CSD Code Filter Processor Unit in CMOS -- S. Hentschke, A. Herrfeld, D. Forster, M. Heinemann, and R. Wicke
An Implementation of a Large Array of Non-linear Data Processor Elements using FPGA's -- C.T. Pointon
Deeply Embedded Handwriting Recognition -- J.Y. Brunel and M. Hervieu
ASIC Design and Implementation of an Associative Memory Processor for Syntactic Recognition -- Nelson Correa, A. Garcia, H. Burbano, and W. Ricaurte

SESSION 8: ASICs For Data Computing

Session Summary -- Dave England, Chair

A Digital CMOS Programmable Clock Generator -- P.T. Holler and H. Lee
Design of an ASIC for Digital Audio Signal Level Meters -- Shugang Wei and K. Shimizu
Low Voltage, Low Power 13 Bit Linear Voice CODEC With Programmable Analogue Front End -- Drago Strle, A. Pletersek , K. Riedmuller, and T. Karema
A Self-timed Interrupt Controller: A Case Study in Asynchronous Microarchitecture Design -- Alessandro De Gloria, P. Faraboschi, and M. Olivieri
Topologically Flexible and Highspeed Network (ToF-Net) -- Hidetoshi Matsuoka, F. Hirose, and S. Shimogori
An ASIC for Wideband Signal Processing in Electronic Warfare Systems -- R.J. Inkol, M. Exonu, D.Al-Khalili, L. Desormeaux, and V. Szwarc
Efficient Allocation Method of Multiport Memories in ASIC Datapath Synthesis -- Kwany-soo Seo
A 200-MHz CMOS Bit-Serial Neural Network -- H. Johansson, P. Larsson, Per Larsson-Edefors, and C. Svensson

SESSION 9: Simulation and Modeling

Session Summary -- Jim Barby, Chair

Recent Developments in Simulation -- Albert Davis
Behavioral Modeling Techniques for Analog and Mixed-signal Design -- Prasad Subramaniam
Model-Adaptable MOSFET Parameter Extraction Method Using a Common Intermediate Model -- Masaki Kondo, H.Onodera, and K. Tamar
Simultaneous Switch Noise Modeling for High Performance ASIC -- Bernhard Andersen, R. Martin, S. Keeney ,S. Schenck and R. Phelps
A VLSI Design and Cost Analysis of Broadband ATM Switch Elements -- Hon Shi, D. Ennis, S.Fernandez, C. Zukowski and O. Wing

SESSION 10: Physical Implementation of Systems

Session Summary -- Thaddeus Gabara, Chair

Package and Test Techniques for Known Good ASIC Die -- Richard W. Chrusciel
LAXTER, a New Method for Extraction of Parasitic Effects from MCM Layout -- Arzu Simsek, Q. Luo, and A. Eder
50,000 gate ASIC prototyping PLD using Four Flex 8000 Devices and a Programmable Interconnect -- Richard Terrill
A Modular, High Performance, 2um CCD-BiCMOS Process Technology for Application Specific Image Sensors and Image Sensor Systems on a Chip -- R.M. Guidash, P.P.K. Lee, J.M. Andrus, A.S. Cicarelli, H.J. Erhardt, J. Fisher, E.J. Meisenzahl, P.H.Phil-brick, and G. Ting

SESSION 11: Test

Session Summary -- Morris Chang, Chair

Characterization of Opens in Logic Circuits -- Jeffrey S. Rogenski, F. Joel Ferguson
An Analysis of Shorts in CMOS Standard Cell Circuits -- Alvin Jee
A Fault Coverage-Driven Partial Scan Chain Selection Technique -- Clay Gloster
Dynamic Power Supply Current Monitoring of SRAMs -- Shyang-Tai Su, R. Z. Makki and H.T. Nagle

SESSION 12: Circuit Architecture

Session Summary -- Al Chiang, Chair

Benchmarks Reveal Performance and Capacity Tradeoffs of Programmable Logic Devices -- Stephen Kliman
Synchronous Performance and Reliability Improvement in Pipelined ASICs -- Eby Friedman

SESSION 13: Test II

Session Summary -- Clay Gloster, Chair

Implementing a CMOS Boundary-Scan Architecture Tutorial -- Bibiche Geuskens, and K. Rose
On Choosing the Right Error Models for Circuit Testing -- Robert Stave, D. Kao, and T.Y. Lin
An Efficient Approach to Low Cost Sequential Circuit Testing in BIST Environments -- Chien-In Chen, F. O'Bleness
Analog Built-In Self-Test -- Mohammad S. Nejad, L. L. Sebaa, A. Ladick, H. Kuo
Behavioral Fault Simulation and ATPG System for VHDL -- Tim H. Noh, C. Chen, and S.M. Chung
An Efficient Tree-Based Algorithm for Computing Path Delay Fault Coverage -- Bhanu Kapoo and V.S. Sukumaran Nair
A Study of Pipelined Pseudo-Exhaustive Testing on VLSI Circuits with Feedback -- Huoy-Yu Liou, T.Y. Lin, and C. Cheng

SESSION 14: ASICs for Telecommunications

Session Summary -- Hyun Lee, Chair

FPGA Prototype Queuing Module for High Performance ATM Switching -- H. Duan, J.W. Lockwood, and S. M. Kang
A Single Chip RSA Processor Implemented in a 0.5mm Rule Gate Array -- Shinji Ishll, K. Ohyama, and K.Yamanaka
A Single Chip Multiprocessor DSP Solution for Communication Applications -- David Regenold
A VLSI Processor Design of Real Time Data Compression for High Resolution Imaging Radar -- Wai-Chi Fang, P. Renick, M. Paller, and W. Johnson
Four Channel DS1 Framer -- Eugene L. Parrella and S.M. Chang

SESSION 15: Special Topics

Session Summary -- Robert Inkol, Chair

A Fast Logarithm Converter -- Guenter Knittel
Pipelined 50 MHz CMOS ASIC for 32 Bit Binary to Residue Conversion and Residue to Binary Conversion -- Sathi Perumal and R. Siferd
A 60 MHz ASIC for ASIC for B-bit Serial/Parallel Multiplier -- Farook Moogat and R. Siferd
Design of a Processor Bus Interface ASIC for the Stream Memory Controller -- Sean McGee, J. Aylor, R.H. Klenke, and A. Schwab
A Low-Cost, Smart-Power BiCMOS Driver Chip for Medium Power Applications -- Goodwin Ting, R.M. Guidash, P.P.K. Kee and C. N. Anagnostopoulos
A High Performance SRAM-based FPGA Device -- Fred Slotnick, P. Butler, W. Li, D. Tang, and M. Shieh
Second Generation ORCA Architecture Utilizing .5um Process Enhances the Speed and User Gate Capacity of FPGAs -- Barry K. Britton, Yaw T. Oh, William Oswald, Ho T. Nguyen, Satwant Singh, Chong Lee, Wai-Bor Leung, Carolyn Spivak, Jim Steward and C. T. Chen