It is with genuine pleasure that the Program Committee welcomes your participation in the Seventh Annual IEEE International ASIC Conference and Exhibit. The conference offers a unique opportunity to learn many of the latest advances in ASIC technology that will impact research and development and indicate future trends.
The conference starts Monday with two days of our very popular workshops. Last year's survey of workshop attendees overwhelmingly endorsed the hands-on nature of these sessions. As a result, we have once again tried to provide a mix of lecture and workstation use during the session throughout the eight workshops.
The technical sessions begin on Wednesday morning and run through Friday noon. Our keynote speaker is Dr. Ronald Smith, Intel Corporation, General Manager, PCI Components Division. The 110 papers and 12 tutorials selected by the committee will be presented in 15 sessions. Three sessions will run in parallel Wednesday afternoon and Friday morning; four more parallel sessions will run Thursday. The presentations have been arranged in 20-minute time slots with a 30- minute break every morning and afternoon. Author interviews will take place immediately following the sessions.
The conference banquet is set for Wednesday evening. Our speaker is Mr. Bob Pease, National Semiconductor. Later that evening is a panel session on "Reversible Adiabatic and Conservative Devices. Cold Fusion of Electronics? or Hope for the Future?"
The conference luncheon will be held on Thursday. The speaker will be Arpad G. Toth, Image Telecommunications Center, Eastman Kodak Company. Immediately following the technical sessions on Thursday is a cocktail reception in the exhibits area.
We extend a special thank you to the members of the Technical Program Committee and Organizing Committee. These committees are composed of volunteers from industry and universities from all over the world. The success of the conference is a direct result of their hard work and dedication. We thank the authors of the papers, tutorials and workshops for the high standards of their work, and the exhibitors for being an integral part of the conference by displaying state-of-the-art ASIC tools, technology, and services.
Sincerely,
Paul Lee, Conference Chairman Subhash Roy, Technical Program Chairman Peter Parslow, Exhibits Chairman
With the mass production of personal computers, the PC has found widespread use just like its predecessors: telephones and television. By the turn of the century, the PC's of today will evolve into a 1000 mips, 16MB cache, 2 GB disk portable machines. Better graphics and asynchronous mode transfer technology will enhance the performance of multimedia applications and provide the telecommuters and home office users with a powerful communication infrastructure.
The power of mass produced PC's and communication bandwidth are now interdependent. Digital technology and standards will power the moves to tie PC's in to existing satellite, cable and ISDN networks. Digital storage devices and interface providers need to become widely integrated to external infrastructures to access information via the information highway.
Convergence of media, network and industrial application via digital technology presents unique challenges to designers and tool developers. The need for smaller and faster machines with better video, graphics and networks will continue to grow. Approximately 90% of present PC computing mips were installed in just the last two years. Submicron technologies and VLSI integration will play a critical role in meeting these challenges.
To accelerate growth based on growing requirements, ASIC designers must meet the challenge of developing complex 500,000 gate, 150 MHz, low cost, low power sub-micron devices that do not require the current simulation/verification paradigm. The infrastructure for development of such devices will need formal verification and correct by construction systems. ASIC and system designers will face the challenge of converting PC into a ubiquitous information device.
Ron Smith has been with Intel Corporation for 16 years. He is currently General Manager of PCI Components Division. Prior to this, he served as the General Manager of Programmable Logic Device Operation and Gate Array Operation. He has also served as the Manager of Intel's logic process technology development, including Intel's first CMOS processor on which the original 80386 was fabricated. Ron holds an M.S. and Ph. D. in Physics from University of Minnesota and a BA from Gettysburg College, PA.
What's all this feedback stuff anyway?? This talk will discuss many different kinds of feedback including digital, analog, sociological, and animal. Feedback in terms even an ASIC designer can understand.
Robert A. Pease was born August 1940 in Rockville, Connecticut. He attended Mount Hermon School and graduated from MIT in 1961 with a BSEE degree. He was employed at George A. Philbrick Researches from 1961-1975 and designed many Operational Amplifiers, Analog Computing Modules, and Voltage-Frequency Converters.
Pease joined National Semiconductor in 1976. He has designed several analog ICs including power regulators, voltage references, Voltage-to-Frequency Converters, temperature sensors, and amplifiers. He has written about 60 magazine articles and holds about 10 US Patents. Pease is the self-declared Czar of Bandgaps since 1986. He enjoys hiking, hack-packing, and following abandoned railroad roadbeds. He also designs Voltage-to-Frequency converters in his spare time.
Pease has written the definitive book, TROUBLESHOOTING ANALOG CIRCUITS (published by Butterworth-Heinemann, May 1991), now in its third printing. He is also a columnist in Electronic Design magazine, with over 90 columns published. The column, PEASE PORRIDGE, covers a wide range of topics and was awarded a Certificate of Merit from the Jesse II. Neal Awards Committee of American Business Publications, in March 1992.
Rapid advancements in telecommunications, microelectronics, signal processing, computing and mass production of highly complex communication and computing oriented devices to the consumer market have established unique opportunities for creating large number of image/video-intensive telecommunication applications.
Digital television broadcast and digital two-way video communications have become viable for wide-spread penetration at various image quality levels and bit rates (e.g., MPEG, digital high definition television /HDTV/, videophone). Digital stationary image storage, playback and transmission techniques at varying quality levels have resulted in commercially viable imaging system solutions and applications (e.g., Photo-CD, JPEG)
Low cost integration of computing, image/video and telecommunication platforms and new display techniques permit the creation of new forms of end-user devices: smart-TV, intelligent cable-TV settop box, multimedia-PC, etc. The advances in these end-user platforms are so rapid that they are quickly becoming obsolete. New generation TV's, settop boxes and PC's become communications enabler for other consumer image/video devices (e.g., printer, electronic camera, storage/play-back peripheral, etc.)
From the commercial point of view, implementation of single -killer application" can no longer be the goal. Instead, groups of image/multimedia applications will create the expected revenue to network, services, media and platform providers. In this environment, harmonization of digital image/video/multimedia for all forms of information applications is critical. There is need to agree on a range of system parameters and characteristics that are not specifically application-oriented. These parameters may include colorimetry, pixel aspect ratio, compression, resolution, image encoding and image data identifiers. interoperability, extensibility, scalability and more generally "openness" are ascribed to devices, appliances, applications, systems that can effectively "cope" with an array of alternatives. Devices/systems with these characteristics allow operation in such a way that image impairments are minimized to the viewer.
The focus of business and technology development will shift from hardware and software platforms towards applications, information content, services and media. The key enablers of the "information superhighway" are: fully open network and access solutions to communicate in any desired form including point-to-point, multipoint and broadcast; open access to all types of information service providers globally; easy access to network intelligence to serve multitudes of end-user demands; seamless interoperability across applications, communication services, media and hardware plus software platforms; scalable application dependent features and technical characteristics of platforms and network resources under end- user control.
The information superhighway will have physical and logical components. The application implementation must be extremely user-friendly. Powerful computing resources will be made available for all forms of communications applications. Maturing image science techniques will strongly influence the creation, search, retrieval, storage and presentation of information. Image and video telecommunications will soon become a part of every day's life.
The superhighway should evolve such that it preserves competition in the traditional sense, and it fosters the flow of all types of new and archive information without technical and regulatory bottlenecks. The information superhighway will likely support the creation of entire new skills and industries around it. The task to build this new communication infrastructure requires unprecedented collaboration of multi-billion dollar industries. Numerous strategic alliances and partnering relationships between multiple industries have already been built. Mergers, takeovers and acquisitions are typical signs of the emerging business opportunities. The stakes are high so are the rewards. Participation in this evolution requires real skills and industry leadership.
Arpad Toth joined the Imaging Research Laboratories of Eastman Kodak Company in 1991. He is the Image Telecommunications architect at the Image Telecommunications Center leading systems planning and development of new generation digital image telecommunication architectures, telecommunications access protocols, interfaces and solutions for specific commercial image applications. In a parallel capacity, Arpad is a Marketing Executive in building new Kodak relationships within the telecommunication industry.
Prior to joining Kodak, Arpad was with Philips Laboratories in Briarcliff Manor, New York between 1986 and 1991. He was chief scientist of the Laboratories responsible for advanced television technology and strategic planning, and multi-resolution digital video communication systems and multimedia research. From 1977 to 1986, Arpad was with BellNorthern Research, both at its central research laboratories in Ottawa, Canada and the Research Triangle Park, North Carolina facilities. His responsibilities included exploratory research in fiber access systems, HDTV and management of broadband access network planning for integrated services voice, data and video.
Arpad is member of the Board of the Public Broadcast Station in Rochester. He is also member of the Columbia University Industrial Advisory Board for Electrical Engineering. He was chairman of the First and Second International TV Workshops. He was founder and chairman of the Electrical Industries Association Advanced TV Receiver Committee in defining new architecture and interfaces for digital Advanced TV consumer products.
Arpad is a native of Hungary, has graduate degrees in electrical engineering from the Technical University of Budapest and the University of Toronto.
The workshops this year offer a wide range of topics addressing the concerns of the novice ASIC designer (schematic based design with gate level simulation) as well as the experienced ASIC designer (text based design with behavioral simulation). Included are several workshops directed at specific types of ASIC designs and their applications.
The workshops are primarily targeted towards ASIC designers and systems engineers. The aim is to provide the individual with hands on experience oriented towards practical usefulness and application. The workshops are offered over two days with an attempt at scheduling in such a way that the Day Two workshops are a natural follow on to the Day One workshops taking into consideration each individual's various experience level and needs.
The Day One workshop, "Introduction to VLSI and ASIC Design Tools for the Beginner", by Rochester Institute of Technology is a precursor to the Day Two workshops, Testing Digital Circuits and Designing Scan and Self-test" by the University of Texas/IBM Corporation and "Top down VHDL Design" by Viewlogic Systems Incorporated.
Altera Corporation's Day One workshop "Digital Design with VHDL" prepares the student for the Day Two analysis of VHDL workshops by Synopsys Inc. "An excursion into VHDL" and "Experimenting with VHDL".
For the experienced ASIC designer choosing to address particular design issues, Day One workshops, "Designing a Rambus ASIC" by Rambus Inc., and "Ensuring Correct Timing in a High Performance Gate Array" by California Institute of Technology; and the Day Two workshop "Designing a Digital Signal Processor" by Rochester Institute of Technology/Mentor Graphics Corporation, represent two days worth of practical ASIC design and application.
All workshops provide the student with handouts and other related material and most are hands-on (PC or workstation) and presented in a lab environment at a local university with transportation to and from the convention site provided.
This workshop is designed to give the beginning ASIC designers or project managers an introduction to the electronic design automation (EDA) tools, including schematic capture, VHDL capture, FPGA simulation and digital circuit simulation. HP workstations Mentor Graphics' EDA tools, including design architect, quicksim II, quick VHDL, Auto Logic or Synopsys synthesis tools will be used.
The IEEE-1076 standard hardware description language, VHDL, is rapidly becoming a prominent component of the design, documentation, and simulation environment of the electronics industry. This workshop presents an innovative series of tightly coupled VHDL models that will introduce many of the fundamental principles of VHDL.
This workshop explores a set of experiments that both challenge and reinforce the participant's understanding of how the various VHDL constructs behave and interact with each other. Each experiment is self contained and isolates key design issues and caveats based on real- world VHDL coding scenarios.
The goal of this workshop is to introduce the non-VHDL user to the basic concepts of writing synthesizable VHDL descriptions of digital designs. Attendees will begin learning with simple logical descriptions and quickly move towards more useful constructs, such as counters and state machines. The workshop emphasizes a hands-on approach, with roughly fifty percent of the time spent writing VHDL and working with a VHDL synthesis tool. The VHDL synthesis tool that will be used in this workshop is Altera Corporation's MAX+PLUS II, although the concepts of synthesizable VHDL are independent of the synthesis tool, and can be applied to the creation of any VHDL design description.
The focus of this workshop is the testing of digital circuits and those design methods which make testing a simpler task. As logic circuits become larger, faster, and more complex, as boards become more difficult to physically access, and as systems become more difficult to diagnose, the costs associated with testing continue to increase. This workshop will provide practical methods for keeping testing costs at a reasonable level while still providing acceptable confidence in the viability of the units passing the testing process.
This workshop covers the fundamental elements of Rambus technology - a revolutionary new type of memory interconnect which transfers data at 500 MB/s. Attendees will gain a thorough understanding of Rambus memory technology and will be able to design an ASIC memory controller optimized for the Rambus architecture using the Rambus ASIC interface macro cell (RAC). Documentation and design examples will be provided, along with a description of Toshiba's ASIC design flow incorporating the RAC macro cell.
The workshop will explain the various methods for meeting the timing requirements of a design using sub-micron CMOS or GaAs gate arrays, without iterating on Place-and-Route. Modern techniques such as Intelligent Front Annotation and Hierarchical Floor-planning will be discussed. The workshop is not vendor specific. Workshop notes will be provided.
The workshop will concentrate on the specification, simulation and implementation of Digital Signal Processing (DSP) systems with Mentor Graphics DSP Station. The full range of commercial DSP processor solutions to ASIC implementations will be covered. Hands-on experience is possible with two examples describing a simple and a more complex system. Workshop handouts and example descriptions will be provided.
The workshop will demonstrate how to effectively use VHDL to get the best synthesis results. Starting with a VHDL behavioral abstraction of a design, the workshop will introduce architectural synthesis and VHDL simulation as a approach to quickly and effectively explore performance tradeoffs associated with different architectural implementations. The design will then continue through the synthesis process, where we will explore the various types of control you have over the gate level synthesis process, including timing optimization, and tradeoffs between speed and area optimization.
The ASIC Conference will hold 12 tutorial sessions, scheduled throughout the conference. They are designed to educate attendees and complement the paper presentations.
2:50 p.m. Behavioral Modeling for Top Down Mixed Signal Design
(T6) Prasad Subramaniam
40 min. AT&T Design Automation, Murray Hill, NJ
3:35 p.m. Synchronous Performance and Reliability Improvement in Pipelined ASICs (T9) Eby Friedman 60 min. University of Rochester, NY
9:10 a.m. On Choosing the Right Error Models for Circuit Testing
(T11) Ting-Ting Lin
40 min. University of California at San Diego
Wednesday 10:15 - 11:45 a.m.
Architectures for VLSI Video Processing
Emerging multimedia applications based on video signal processing require processing in the range of 100-10K MIPS supplied by silicon costing less than $400. This combination of price and performance would argue for a full custom dedicated architecture. The pace at which the marketplace is changing, however, combined the variety of new products and services being proposed calls for programmable architectures in which a common hardware platform can be used to rapidly bring new products to market based on software development only., This talk will examine the various operations required by video signal processing applications and explore the architectural options open to the designer. Examples of commercial architectures will be used to highlight the strengths and weaknesses of these various approaches.
ADC and DACs: Practical Techniques and Limitations
An overview of the techniques of ADC and DAC circuits as implemented in monolithic devices. Which have been the most successful and why? Review of the Circuit techniques that overcome some of the limitations. With the advent of VLSI Analog parts can other solutions to these old problems be found?
ASICs, CAD, and Emerging Applications
Progress in ASICs and progress in CAD are closely interdependent and three new developments are currently driving the evolution of ASIC CAD. The first two are traditional--the new physical effects of deep submicron processes and the complexity issues arising from rapidly increasing gate counts. The third development, and the main focus of this talk, is the use of ASICs in new applications such as wireless, portable and high-speed telecommunication. New and improved CAD tools and design methodologies are needed to take full advantage of ASICs in such environments.
Over the last year or two, efforts have been focusing on the possibility of performing low power logic calculations using a new circuit technique incorporating the principles of thermodynamically reversible devices. This technique offers the potential of reducing the power dissiaption of IC circuits by an order of magnitude or more.
The potentials could allow portability of complex systems to become a reality by extending the lifetime of energy sources several fold.
Is the concept of themodymically reversible devices feasible? This session hopes to address this issue to see if these circuit techniques are possible.
PANELISTS:
Jeff Everts, Chair
Sandia National Laboratories
1:25 p.m. Session Introduction
1:30 p.m. A Mixed-Signal ASIC for Piston Temperature
Measurement in Internal Combustion Engines
(p1-1 ) Eric G. Chowanietz
De Montfort University
Thermal monitoring of reciprocating parts of internal combustion engines relies on telemetry from the moving piston to a fixed point on the engine block. This paper presents a piston-mounted data-acquisition ASIC that transfers data via an infra-red link and is energized by a high- frequency inductively-coupled power-supply.
1:50 p.m. An Electro-Optical Standard-Cell for ASIC
Design
(p1-2) Sihin Seyfou and Richard J. Auletta
George Mason University
The application and design of an integrated electro-optical digital system for optically accessed database machines is described. The electro-optical cell is integrated into the standard-cell process using VHDL as the language for system specification. The numerical inequality detection circuit is also implemented on the same chip.
2:10 p.m. A Word/Bit Parallel Inexact Match Content
Addressable Memory
(p1-3) W. Robert Daasch and Jack Lee
Portland State University
This presents a new content-addressable-memory (CAM) that evaluates the Hamming distance to a multi-valued signal and permits a bit-level fine-grained parallel search of the entire memory. This technique reduces the 1Kx16 RAM search of 16,000 operations (worst-case) to one operation.
2:30 p.m. A 1-MHz and 16-bit "sigma""delta" DAC
With a 224th-Order Reconstruction FIR-Filter Using Only 9 Nonzero
Taps
(p1-4) Christer Jansson and Christer Svensson
Linkoping University
This paper presents a 6th-order digital-to-analog sigma-delta converter with an integrated FIR filter with nine non zero taps as part of the reconstruction filter. The results of the fabricated 1 mm CMOS ASIC are presented.
2:50 p.m. A Dual-Channel Analog Servo-Signal Processor
for 13GB Tape Drive
(p1-5) Sriram Narayan and Hans W. Klein
IMP, Inc.
This paper describes the first dual-channel analog signal processor for servo control in a 13Gbyte QIC tape drive systems. The highly programmable low-power, low-cost CMOS IC provides 12 bit accuracy employing sophisticated real-time peak-detection, error correction, and calibration. It provides both analog and digital servo information, servo motor control and built-in analog test capability. Innovative circuit implementations presented here include a high-bandwidth VGA and a peak-detector with clock recovery which removes the need for on-chip PLLs. Behavioral modeling of the entire chip was used to ensure system integrity.
3:10-3:35 p.m. Break
3:40 p.m. An Analog VLSI Neural Network for Real-Time
Image Processing in Industrial Applications
(p1-6) M. Valle, M. Onorato, F. Oddone, G.M. Bisio, DD. Caviglia
University of Genova, Italy
Fluorescent magnetic particle inspection (FMPI) is a commonly used technique in non-destructive testing. Neural networks can be used in the classification process. In this paper such an algorithm has been implemented in VLSI-based analog circuit design. In this work the computational primitives are completely analog, whereas the long term storage of the weights is in digital form.
4:00 p.m. Multi-GHz CMOS Oscillators
(p1-7) Thad Gabara, W.Fischer
AT&T Bell Laboratories
An Oscillator circuit has been designed in CMOS that operates at 5.2 GHz range. The power has been reduced to 10% that of conventional CMOS technique by use of inductors to form a tank circuit, driven by coupled CMOS inverters. The frequency of oscillation is insensitive to chip parameter variation.
4:20 p.m. A CMOS Low Voltage High Performance
Interface
(p1-8) J.D. Trotter, S. Rekhi, V. Chava, and P Kale
Mississippi State University
The implementation of a low-voltage interface suitable for both serial and parallel communication is presented. This design incorporates self-correcting pull-up and pull-down resistances, and also supports interfacing of CMOS to heterogeneous logic such as ECL. Two test chips have been fabricated and tested. A summary of the results are presented.
4:40 p.m. Constant Delay Logic Technology
(p1-9) David W. Hall, J.G. Dooley, and A. Hernandez
Harris Government Aerospace and Communication
Systems Divisions
A low-noise logic (LNL) family has been developed for use in embedded COMSEC applications to reduce switching transient disturbances on power supply distribution and reduce the coupling between adjacent interconnect metal. An asynchronous, digital-delay line may be constructed that is more robust than using a string of inverters.
Scott Baker, Chair
Genesis Microchip
William Cook, Co-chair
Eastman Kodak Company
1:25 p.m. Session Introduction
1:30 p.m. Combining the Top-Down Approach with
Bottom-Up Advantages in Logic Synthesis
(p2-1) Volker Keifer
Motorola Inc.
Evolution from bottom-up to top-down strategies has brought many advantages to the ASIC design community. High Level synthesis is especially geared towards the top-down style. However, the top-down approach does not automatically capitalize on complex elements in the ASIC library. This paper proposes a new method to exploit these elements during logic synthesis
1:50 p.m. Scheduling in the Presence of Conditional
Constructs and the Optimization of Control
Structures
(p2-2) Jon Ainscough
Manchester Metropolitan University, U.K.
Recently, researchers are extending current scheduling techniques to enable VHDL processes to be synthesized so that they execute in parallel. This paper demonstrates that complex control structures can be scheduled as a single entity thereby exploiting the parallels in, across, and within the individual process structures.
2:10 p.m. Structure Exploration in High-Level Language
Description for Logic Synthesis
(p2-3) Yulin Chen
Hitachi Micro System, CA
This paper presents a new idea in handling the information flow between high-level RTL description and logic synthesis. The objective of this approach is to optimally synthesize a circuit by dynamically changing the logic synthesis script based on the circuit regularity which is more visible in high-level language description than in low level logic design and circuit structure.
2:30 p.m. Exploring ASIC Design Space at the System
Level with a Neural Network Estimator
(p2-4) Peter Ellervee
Royal Institute of Technology, Sweden
Estimators are critical tools in doing architectural level exploration of the design space and system partitioning between hardware and software. This paper presents a novel approach to estimation based on a multilayer feed-forward neural network. We present results from experiments with the first model of a neural network based estimator to choose the base architecture of the network.
2:50 p.m. Synthesis of Memories from Behavioral HDLs
(p2-5) Nels Vander Zanden
Compass Design Automation, CA
This paper describes a new approach for synthesizing small memories, such as multi-port register files, from behavioral HDLs. The techniques provide more compact HDL descriptions of designs by allowing behavioral descriptions instead of structural instantiations. In addition, the designer can experiment with multiple architectural implementations for the memory without changing the HDL description
3:10-3:35 p.m. Break
3:40 p.m. High Level Synthesis in DSP ASIC
Optimization
(p2-6) Jouni Isoaho
Tampere University of Technology, Finland
Hard constraints in development costs and time-to-market in ASIC design force designers to search for methods to speed up and automate the design process. In this paper, we present how high level synthesis can be used for optimization of DSP ASIC design.
4:00 p.m. A Microprocessor in Four-Month Development
of the FHOP
(p2-7) Thomas Gieringer
ASIC Design Center, Offenburg, Germany
As the number and complexity of ASIC design increases, there is a
strong need for implementable reusable cores as compact and proofed
macrocells. This paper presents the design of a microprocessor kernel
macro cell using VHDL and logic synthesis, completed in only four
months.
Ramalingam Sridhar, Chair
University of Buffalo
Al Chiang, Co-chair
Brooktree Inc.
1:25 p.m. Session Introduction
1:30 p.m. A Pass Transistor Regulator Structure for
Implementing Multi-Level Combinational
Circuits
(p3-1) Jose Luis Neves and A. Albicki
University of Rochester
This paper presents a novel approach to the implementation of logic functions with pass transistor logic. A set of pass transistor logic gates that provides a regular and dense layout structure is developed. It permits the inclusion of buffers to maximize circuit speed without disrupting the layout structure
1:50 p.m. CMOS Wave Pipelining using Transmission-
Gate Logic
(p3-2) Xuguang Zhang and R. Sridhar
SUNY at Buffalo
CMOS transmission-gate logic is applied to the implementation of wave-pipelined circuits. Basic circuit cells of the logic, all with similar gate delays have been developed. Simulation results demonstrate significant reduction of the timing delay variations (within 15% of the total path delay) for different input variations.
2:10 p.m. Tapered Buffers for Gate Array and Standard
Cell Circuits
(p3-3) Brian S. Cherkauer and E. Friedman
University of Rochester
CMOS tapered buffers are used to drive large capacitive loads. A methodology for designing optimally tapered buffer systems that considers local stage-to-stage interconnect capacitance is described. Reductions in power dissipation of up to 22% and active area of up to 46% with smaller reductions in propagation delay are demonstrated.
2:30 p.m. Low Power via Reduced Switching Activity and
its Application to PLAs
(p3-4) Razak Hossain and A. Albicki
University of Rochester
In this paper, a number of techniques are presented for reducing the power dissipation in PLAs by reducing its expected switching activity. The application of the techniques to a set of benchmark PLAs results in an average of 14% reduction in switching activity at the internal AND plane gates of the PLA. The method can be extended to other combinational structures.
2:50 p.m. Quasi-Static CMOS
(p3-5) Thad Gabara
AT&T Bell Laboratories
A quasi-static CMOS circuit technique which allows low power consumption has been developed. The circuit can reduce power dissipation by up to 10X over conventional CMOS.
3:10-3:35 p.m. Break
3:40 p.m. A Static Technique for High-Speed CMOS
State Machine Design
(p3-6) Kevin McLaughlin, A. Schwab and J. Aylor
University of Virginia
This paper presents a pseudo-dynamic technique for designing static CMOS high-speed state machines. This technique applies weak feedback to conventional dynamic circuits to achieve both static and high- speed capability. A 21-bit counter using these techniques achieves 100MHz operation.
4:00 p.m. A 200ps 0.5micron CMOS GAte Array Family
with High-Speed Modules
(p3-7) Yoji Nishio, H. Hara, M. Iwamura, Y. Kaminaga, K.Koike, K.
Hirose, T. Noto, Y. Yamamoto and T. Ono
Hitachi, Japan
A 0.5micron 3.3V CMOS gate array/embedded array family is described. Access times of 1Kbit metallized RAM are 3.7ns, and 16K bit diffused RAMs have access times of 3.9ns. Use of these cells and improved GTL structures realize 100MHz operation.
4:20 p.m. A Mixed Asymmetric/Symmetric (MASS)
MOSFET Cell for ASICs
(p3-8) Kouichi Kumagai, S.Kurosawa, H. Iwaki, N. Hamatake, A.
Yoshino, K. Okumura, K. Ohuchi, K.Nakajima, A. Asahina
and Y. Yamazaki
NEC Corporation, Japan
A new CMOS Sea-of-Gates basic cell that embeds mixed asymmetric and symmetric(MASS) LDD MOSFETs has been developed. The paper presents 142K-Gates MASS cell SOG using a 0.5 micron CMOS technology with two additional masks. A 13% improvement in speed is obtained.
Mike Smith, Chair
University of Hawaii
Suhail Issa , Co-Chair
OKI Semiconductor
8:25 a.m. Session Introduction
8:30 a.m. Datapath Cell Design Strategy for Channelless
Routing
(p4-1) Naresh Kumar Sehgal, C. Y. Chen, and J. Acken
Intel Corp, Santa Clara, CA
A methodology is presented for laying out bit-sliced structures using library cells. Layout connectivity techniques are used to meet the high density requirements of datapath design. Individual cells are designed and stored in a library, which in turn is used to design datapath units with full abutment, supporting over-the-cell routing.
8:50 a.m. Synthesizing Distributed Buffer Clock Trees
for High Performance ASICs
(p4-2) Jose Luis Neves and E. Friedman
University of Rochester, NY
A methodology is presented for synthesizing clock distribution networks while exploiting localized non-zero clock skew in order to improve circuit performance and reliability. An optimal clock skew schedule is determined, which minimizes the circuit's clock period. This is used in conjunction with the functional hierarchy to design the clock distribution topology.
9:10 a.m. Optimal Buffered Clock Tree Synthesis
(p4-3) Jae Chung and C.K. Cheng
University of California, San Diego, CA
This paper proposes a clock buffer synthesis algorithm using dynamic programming to find optimum buffer sizes and insertion levels. It also optimizes wire widths in order to further reduce propagation delay and sensitivity to clock skew. Experimental results indicate a significant reduction in both delay and skew sensitivity under manufacturing variations.
9:30 a.m. An Efficient Routing Technique to Resolve the
Current-Crowding Effect in the Power Grid
Structure of Gate Arrays
(p4-4) Chingchi Yao, I. Yamamoto, and S.Nomura
OKI Semiconductor, Sunnyvale, CA
This paper presents a technique to alleviate the current crowding effect in the power grid structure of gate arrays. The proposed power routing technique uses flexible metalization with respect to the power pad locations, resulting in routing structures with improved gate utilization as well as reduced electromigration.
9:50 a.m. High-Performance Routing for Field-
Programmable Gate Arrays
(p4-5) Michael J. Alexander and G. Robins
University of Virginia, Charlottesville, VA
This paper addresses signal delay minimization in FPGAs based on an adaptation of Steiner arborescences to arbitrary weighted graphs, which generalizes Dijkstra's algorithm to incorporate a minimum wirelength objective. Experiments show that this new construction produces routing trees with optimal source-to-sink path lengths, while incurring only a modest wire length penalty.
10:10 - 10:35 a.m. Break
Gabriel Robins, Chair
University of Virginia
Suhail Issa , Co-chair
OKI Semiconductor
10:35 a.m. Session Introduction
10:40 a.m. Computer-Aided Design-Verification Vector
Generation
(p4-6) M. Nance Ericson and C. Stroud
Oak Ridge National Laboratory, Lexington, KY
This paper describes a CAD tool that assists ASIC designers in the generation of design-verification vectors. Interface requirements and operations to be performed during the simulation are described using an assembly language-like format, from which the tool generates the input stimulus and timing relationships for circuit verification.
11:00 a.m. Graphical Specification of Digital Systems
Using Interval Temporal Logic
(p4-7) M. G. Hadjinicolaou, R. B. Hughes, and G. Musgrave
Brunel University, United Kingdom
A graphical interface is proposed, using a timing diagram editor that allows the description of a specification using interval temporal logic. This system combines a formal approach with a convenient user interface that incorporates animation to allow the user to visualize the system behavior.
11:20 a.m. Simple Yet Effective Replication for FPGA
Partitioning
(p4-8) Dinesh Bhatia and V. Narasimhan
University of Cincinnati, OH
This paper deals with the partitioning of large digital designs for
multiple FPGA-based implementation. The approach uses efficient
heuristics for replicating a small number of logic blocks in order to greatly
improve resource utilization. The approach has been integrated with
XILINX APR tools.
11:40 a.m. Hardware/Software Codesign for Digital
Communication Processing
(p4-9) Hakim Saheb and M. Dang
IMAG/LGI, France
An approach for hardware/software codesign is presented for the implementation of digital communication processors. The method is based on an architectural model that performs both real-time and deferred processing. Illustrated by a case study, a new partitioning technique is presented that is based on a timing decision which permits task distribution.
George Brown, Chair
Rochester Institute of Technology
Richard A. Hull, Co-chair
Xerox Corporation
8:25 a.m. Session Introduction
8:30 a.m. VHDL-A: Analog Extension to VHDL
60 min. Richard Shi, E. Christen, P. Liebmann, S. Krolikoski, and
W. Zhou
(T5-1) Analogy, Inc.
VHDL-A is an analog extension to VHDL, currently being developed by the IEEE 1076.1 Working Group under DASC (Design Automation Standards Committee). This tutorial will demonstrate the scope of VHDL-A to support both the description and simulation of digital, analog, and mixed digital and analog systems for both top-down and bottom-up hierarchical design methodologies. It is expected that VHDL-A will go into standardization by early 1994.
9:30 a.m. AHDL Modelling to Support Top-down Design
of Mixed-signal ASICs
(p5-1) J.A. Barby, S.E. Rehan, and M.I. Elmasry
University of Waterloo
With the availability of analog hardware description languages (AHDL) there are new ways of solving mixed-signal simulation and modelling problems. Two top-down modelling approaches for a new mixed-signal Artificial Neural Network (ANN) are presented illustrating how AHDLs are making top-down design of mixed-signal ASICs realistic and the trade-offs involved.
9:50 a.m. Hierarchical Mixed-level Simulation of VHDL
Descriptions
(p5-2) Tanay Karnik, D. G. Saab, S.M. Kang, Y.K. Lee, K.H. Kim
University of Illinois
We present a multi-level VHDL simulator for large systems described at the transistor, gate, and higher levels. The simulation algorithm handles MOS digital designs with bi-directional signal flow. We have augmented VHDL descriptions with signal strengths and timing and propose a method to extend VHDL to accept transistor-level descriptions.
10:10 - 10:35 a.m. Break
10:40 a.m. Macromodeling CMOS Circuits for Event
Driven Simulation
(p5-3) J. Donald Trotter, S. Saripella, D.L. Ledlow, N. Pidugu, D.
Kapoor
Mississippi State University, MS
Traditional approaches to macromodeling and event simulation do not address the changes in propagation delays with the variation of transition times for the inputs. Additionally, the definition of the output event as occurring at the midpoint of the transition can lead to characterized negative propagation delay. Disclosed is a means to circumvent these difficulties and an approach for supporting the timing model in an event simulator.
11:00 a.m. FSM Synthesis on FPGA Architectures
L. Burgun, N. Dictus, A. Greiner, E. Prado, C. Sarwary
(p5-4) Laboratoire MASI/CAO-VLSI Universite Pierre et Marie
Curie, France
This paper addresses the problem of Finite State Machine synthesis for two FPGA architectures: Actel and Xilinx. We propose a unified approach that deals with state assignment, optimization, and mapping problems and takes into account the target architecture during all the phases of the synthesis. This approach is based on Shared, Reduced, and Ordered Binary Decision Diagrams. The results, expressed in number of blocks, indicate that our approach uses 5% for X3090 and 23% for Actel, fewer blocks than the traditional approach implemented by Sis.
11:20 a.m. Performance-Driven Technology Mapping for
LUT-Based FPGAs
(p5-5) Hyunchul Shin, C. Kim, and Y. Yu
Hanyang University, Korea
An iterative optimization technique is developed for technology mapping of lookup-table based field programmable gate arrays. Minimal depth of an optimized Boolean network is found and then the cost function is minimized without increasing the depth. Optimization for reconvergent paths and duplication of logic can be automatically considered. Experimental results are provided.
11:40 a.m. A Systematic Approach in Designing a
Complex System with VHDL
(p5-6) Donald L. Hung
Gannon University
A VHDL-based design procedure for designing a custom hardware fuzzy controller is discussed. The design follows a hierarchical, modularized approach. The controller's architecture is structurally decomposed until the building block circuits can be defined in terms of the Xilinx 4000 family library macros and primitives. With an initial system architecture and the building blocks at hand, the use of VHDL emphasizes system verification rather than synthesis.
Cherrice Traver, Chair
Union College
Nanjunda Shastry, Co-chair
Toshiba
8:25 a.m. Session Introduction
8:30 a.m. Experiences in Teaching ASIC Design Using
Xilinx FPGA & Mentor Graphics Tools
(T6-1) Shih-Lien Lu
20 min. Oregon State University
This tutorial describes an ASIC course utilizing FPGA's. The course syllabus, textbooks and laboratories are detailed. Experiences and successes of this type of instruction are outlined.
8:50 a.m. Education in ASIC Design Using the SET
Concept.
(p6-1) K. Hein & A. Rucinski
Univ of New Hampshire
The Student Engineering Team (SET) concept is outlined. Real
world engineering environment successfully bridges the gap between
academia and industry. This is a proven method for exposing the
engineering student to both the fundamentals of engineering and the
realities of the engineering workplace.
9:10 a.m. Using HYPER to Teach Datapath Design
Techniques in an ASIC Design Course
(p6-2) Bob Reese
Mississippi State University
The integration of the HYPER high-level synthesis tool into an advanced digital design course at Mississippi State Univ. is described HYPER uses the SILAGE language for design specification. This course allows students to explore various design trade-offs of speed, power and size.
9:30 a.m. A Structure of Modern VLSI Curriculum
(p6-3) A. Hemani, M. Mokthari, J. Isoaho,H. Tenhunen
Royal Inst. of Tech. Sweden
A restructuring of the VLSI design curriculum at Royal Institute of Technology to meet the needs of the National industrial base has resulted in a segmentation of the content into separate system level and circuit level profiles. This paper will outline the objectives, content, tools and methods used in the courses that constitute these profiles.
9:50 a.m. A Proposed Training Curriculum in ASIC
Design
(p6-4) M. Mark Farhoomand
AT&T Bell Labs.
This paper proposes a comprehensive curriculum of training courses in the area of ASIC design. This curriculum should serve as a model for educational institutions offering ASIC design courses.
10:10 - 10:35 a.m. Break
Cherrice Traver, Chair
Union College
Mely Chen-Chi, Co-chair
ITRI - Taiwan - R.O
10:35 a.m. Session Introduction
10:40 a.m. A First Pass ASIC Development Methodology
Using Logic Emulation
(p6-6) Thomas Chan, B. Yeh, and Eileen Hu
Apple Computer
This paper describes the use of a logic emulator to verify ASIC functionality prior to fabrication. Logic emulation for ASIC prototyping enables both hardware and software development as well as system verification to proceed in parallel. The development of a printer controller ASIC with first pass success and shortened time-to-market delivery of the printer system is presented.
11:00 a.m. Rapid Prototyping of a Cellular Processor
(p6-7) Vanya Amla and R. Auletta
George Mason University
This paper examines a range of techniques for the design, implementation, and verification of an original architecture for a serial Cellular Automata Machine. The three different approaches examined are: a high-level description using the formal specification language CSP; an intermediate-level structural design in VHDL; and a detailed gate-level design using Logic III. Comparison of the three approaches is provided based on speed, assurance, flexibility of design, ease of design and size.
11:20 a.m. Designing High Complexity ASIC using the
Alliance CAD System
(p6-8) A. Greiner, L. Lucas, and F. Wajsburt
University Pierre et Marie Curie, France
This paper will present the design methodology for a superscaler VLIW microprocessor using the CMOS portable ASIC library developed in the framework of the Alliance CAD system. A full set of portable cell libraries and macro-block generators have been used to achieve a fast design cycle. As well as a high level of integration and performance. This CAD system has been successfully used to design several research ASIC's.
11:40 a.m. Taking Advantage of Reconfigurable Logic
(p6-9) Bradly K. Fawcett
Xilinx, Inc.
The availability of programmable logic devices based on static memory cells allows the implementation of "soft" hardware - that is, logic devices whose functions can be changed while they remain resident in the target system This paper examines three categories of such applications: systems with built-in diagnostic or test logic; "adaptable" system designs; and systems with "multi-purpose" hardware.
Mely Chen-Chi, Chair
ITRI - Taiwan - R.O
Kerry VanIseghem, Co-chair
LSI Logic
1:25 p.m. Session Introduction
1:30 p.m. Tutorial: FPGA Development Tools: Keeping
Pace with Design Complexity
(T6-2) Bradley K. Fawcett
20 min. Xilinx Inc.
As the density and complexity of FPGA-based designs increases beyond 10,000 gates, highly-integrated and automated development tools will be required. Several recent trends in development system capabilities are helping designers meet the twin challenges of growing design complexity and increasing time-to-market pressures.
1:50 p.m. A Methodology for Design Verification
(p6-10) Eileen Hu, B.Yeh, and T. Chan
Apple Computer
This paper documents a methodology that outlines a strategy for successful ASIC design verification. The concept that a verification process be done in parallel with logic design is an improvement over a sequential process. Analysis of design issues are examined and form the basis of the methodology conclusion.
2:10 p.m. Adoption & Utilization of ASIC Technologies in
European SMI's
(p6-11) Tarja Juhola, H. Tenhunen, and I. Nielsen
Royal Institute of Technology , Sweden
This paper examines European surveys that analyze ASIC usage in Small & Medium sized Industries (SMI's). Benefits of ASIC technologies is apparent, however, this paper describes additional methods that may be undertaken to increase adoption and utilization of ASIC's in SMI's.
Mark Schrader, Chair
Eastman Kodak Company
8:25 a.m. Session Introduction
8:30 a.m. A Gradient Processor for High Speed Medical
Imaging
(p7-1) Martin Margala, N. Durdle, S. Juskiw,
V. J. Raso and D. Hill
Electrical Engineering Department, The University of Edmonton, Canada
A processor to calculate normalized direction and magnitude gradients used to display reconstructed tomography or nuclear magnetic resonance imagery is presented. The architecture combines a high degree of parallelism with optimized algorithms for 30 MHz throughput (simulation results).
8:50 a.m. A Fast Reed-Solomon and Cyclic Redundancy
Check Encoding Algorithm for Optical Disk
Error Control
(p7-2) Rom-Shen Kao and V. Gibbs
Mitsubishi Semiconductor America Inc.
An encoder for both Cyclic Redundancy Check (CRC) And Reed- Solomon (RS) codes is developed for optical disk storage. Three architectures are modeled using Verilog HDL and the fastest implemented in 0.8 mm 2 Al CMOS technology. The resulting ASIC is 3 times faster than traditional implementations.
9:10 a.m. A VLSI Design for Full-Search Block Matching
Motion Estimation
(p7-3) Seung Hyun Nam
Yonsei University
A VLSI architecture to achieve a real time processing of full-search block match algorithm (FBMA) for motion estimation is presented. Using a parallel algorithm based on partial result accumulation, partial sum results from candidate blocks are individually accumulated for each distortion measure.
9:30 a.m. Implementing a Digital Signal Processor for an
Electronic Still Camera Using Multiple--FPGA's
(p7-4 ) Sin-shuh Wang and T Chung
Industrial Technology Research Institute Opto-
Electronics & Systems Lab, Taiwan
A digital signal processor (DSP) for an electronic still camera has been implemented in multiple field programmable gate arrays (FPGA). The DSP generates luminance and chrominance signals from a single CCD imager incorporating a complementary color filter array; and provides black-level compensation, gamma correction, color matrixing, and image filtering operations.
9:50 a.m. A Flexible Repetative CSD Code Filter
Processor Unit in CMOS
(p7-5) S. Hentschke, A. Herrfeld, D. Forster, M. Heinemann,
and R. Wicke
IPM University Kassel, Germany
A filter configurable for audio and video applications is (test) implemented in 1.5mm CMOS. The serial design uses canonical signed digit coefficients to reduce the number of necessary additions, and contains 4 filter modules that can be connected to form either an 8, 16, or 32 bit transversal filter or an 8 bit recursive filter.
10:10 - 10:35 a.m. Break
10:40 a.m. An Implementation of a Large Array of Non-
linear Data Processor Elements using FPGA's
(p7-6) C.T. Pointon
School of Engineering, Staffordshire University, England
A re-configurable non-linear data processor array has been designed and implemented using FPGA technology. This realizes the mathematical model of a simplified switching exchange. The design demonstrates the complex dynamic behavior predicted by the model.
11:00 a.m. Deeply Embedded Handwriting Recognition
(p7-7) J.Y. Brunel and M. Hervieu
Laboratories d'Elecronique Philips, France
An neural network classifier ASIC for handwriting recognition in
Personal Digital Assistants
(PDA) has been developed. The classifier can
be synthesized for various levels of performance. An implementation in
0.8 mm technology resulted in a 200 characters per second (95% correct)
recognition rate.
11:20 a.m. ASIC Design and Implementation of an
Associative Memory Processor for Syntactic
Recognition
(p7-8) Nelson Correa, A. Garcia, H. Burbano, and W. Ricaurte
Universidad de los Andes, Bogota, Columbia
A syntactic recognition (associative) co-processor for context-free grammars has been designed for the IBM PC-AT bus using multiple ASIC's. The design uses the single-instruction multiple-data stream (SIMD) capability of a full-custom content addressable memory (CAM) ASIC, and multiple FPGA/PLD's. This design achieves enhanced performance over van Neumann architectures.
Dave England, Chair
Intel Corporation
1:45 p.m. Session Introduction
1:50 p.m. A Digital CMOS Programmable Clock Generator
(T8-1) P.T. Holler and H. Lee
20 min. AT&T Bell Labs
This tutorial explains the transition from analog concepts to digital design using a CMOS software programmable clock generator as an example. The goal of the design was to provide a variable clock rate from 20 KHz to 100 MHz in order to minimize system power.
2:10 p.m. Design of an ASIC for Digital Audio Signal
Level Meters
(p8-1) Shugang Wei and K. Shimizu
Gunma University, Japan
A new design method for audio signal level meters is presented. The design uses a digital approach to monitoring audio signal levels by driving an array of light emitting diodes (LED). A gate array of about 760 gates was used to implement a 7-stage digital audio signal level meter for eight channels in a large scale digital audio system.
2:30 p.m. Low Voltage, Low Power 13 Bit Linear Voice
CODEC With Programmable Analogue Front End
(p8-2) Drago Strle, A. Pletersek ,K. Riedmuller, and T. Karema
University of Ljubljana, Austria
A software programmable low voltage, low power 13 bit linear voice CODEC is presented. This device has an analog front end interface which includes a programmable gain control. The voice band signals are represented in a PCM 2's complement 13 bit linear format. The CODEC is realized in a 1.2MM CMOS technology
2:50 p.m. A Self-timed Interrupt Controller:
A Case Study in Asynchronous Microarchitecture Design
(p8-3) Alessandro De Gloria, P. Faraboschi, and M. Olivieri
University of Genoa, Italy
This paper gives Details of an interrupt controller design that interfaces to an asynchronous microprocessor. The interrupt controller was designed for the SGS-Thomson ST9 family. The controller behavior is described with a CSP program. The 1500 transistor ASIC is fabricated in a 1.2mm CMOS technology.
3:10 - 3:35 p.m. Break
3:40 p.m. Topologically Flexible and Highspeed Network
(ToF-Net)
(p8-4) Hidetoshi Matsuoka, F. Hirose, and S. Shimogori
Fujitsu Laboratories, LTD
This paper proposes a new network architecture (ToF-Net) that allows topological flexibility and high speed communication. ToF-Net is used for inter-cluster communication. It can accept and deliver packets at 4.96 GB/s. It also describes an ASIC that is used to interface to the network.
4:00 p.m. An ASIC for Wideband Signal Processing in
Electronic Warfare Systems
(p8-5) R.J. Inkol, M. Exonu, D.Al-Khalili, L. Desormeaux and
V. Szwarc
Defence Research Establishment Ottawa , Ontario,
Canada
An ASIC designed to process 8 bit data sampled at 400 MHz in electronic warfare (EW) systems is described. It performs functions that include digital quadrature demodulation and signal detection. A high performance is achieved by the implementation of an architecture embodying considerable parallelism and pipelining on a GaAs gate array. The hardware complexity is minimized by careful cost-performance tradeoffs in the design of the quadrature demodulation algorithm.
4:20 p.m. Efficient Allocation Method of Multiport
Memories in ASIC Datapath Synthesis
(p8-6) Kwany-soo Seo
Yonsei University, Korea
This paper proposes a method for allocating multiport memories in ASIC Datapath synthesis. It minimized hardware costs on the basis of a 0- 1 Integer Linear Programming (ILP) model. The objective of the proposed approach is to allocate variables into a minimum number of multiport memory modules and to minimize the number of registers in each memory module simultaneously.
4:40 p.m. A 200-MHz CMOS Bit-Serial Neural Network
(p8-7) H. Johansson, P. Larsson, Per Larsson-Edefors, and C.
Svensson
Linkoping University, Sweden
This paper presents a 200 MHz CMOS bit-serial neural network ASIC device. It is specially designed for a high performance small-area system. This device employs several techniques to obtain low power consumption and high bandwidth.
Jim Barby, Chair
University of Waterloo
Bill Richards, Co-chair
MCNC
1:45 p.m. Session Introduction
1:50 p.m. Recent Developments in Simulation
(T9-1) Albert Davis
60 min. Rochester Institute of Technology
This tutorial presents an overview of recent developments in simulation. It will review the traditional SPICE techniques then introduce the more recent work including relaxation, wave form relaxation, asymptotic wave form evaluation.
2:50 p.m. "Behavioral Modeling Techniques for Analog
and Mixed-signal Design
(T9-2) Prasad Subramaniam
40 min. AT&T Design Automation
A methodology for developing analog and mixed-signal behavioral models for a top-down mixed-signal design environment is presented with the objective of familiarizing analog designers with higher level modeling. After discussing the mathematical concepts, sample models for opamps, analog comparators, ADCs, DACs, PLLs, continuous and discrete time filters will be discussed.
3:10 - 3:35 p.m. Break
3:30 p.m. Model-Adaptable MOSFET Parameter
Extraction Method Using a Common
Intermediate Model
(p9-1) Masaki Kondo, H.Onodera, and K. Tamar
Kyoto University, Japan
This paper presents an efficient parameter extraction method which is applicable to many MOSFET circuit simulation models such as Levels 2, 3, and BSIM1. Key to the methodology is the procedure for initial value estimation by way of a common intermediate model. This framework significantly reduces the amount of time and cost of adapting a newly introduced advanced MOSFET model.
3:50 p.m. Simultaneous Switch Noise Modeling for High
Performance ASIC
(p9-2) Bernhard Andersen, R. Martin, S. Keeney ,S. Schenck
and R. Phelps
Texas Instruments, Dallas
This paper presents a statistical characterization technique, based on a 21-term polynomial equation, to predict switching noise and estimate the number of ground and Vcc pins required to meet noise requirements.
4:10 p.m. A VLSI Design and Cost
Analysis of Broadband ATM Switch Elements
(p9-3) Hon Shi, D. Ennis, S.Fernandez, C. Zukowski and O.
Wing
Columbia University, New York
For the design of an ATM switch, the objective is to find switch design parameters to meet the system requirements. The conventional design approach is an iterative, time consuming procedure, making it difficult to find optimal solutions because of the large variable/solution space. This paper proposes a novel design approach based on non- linear optimization and VLSI modeling.
Thaddeus Gabara, Chair
AT&T Bell Labs
Shih-Lien Lu, Co-Chair
Oregon State University
2:35 p.m. Session Introduction
2:40 p.m. Process and Test Techniques for Known Good
ASIC Die
(T10-1) Richard W. Chrusciel
40 min. ETEC
This tutorial will discuss four methods of mounting die into temporary packages that allow full parameter and temperature range testing to be performed. Each method will be evaluated for cost, as well as its impact on electrical parameter performance.
3:10 - 3:35 p.m. Break
3:40 p.m. LAXTER, a New Method for Extraction of
Parasitic Effects from MCM Layout
(p10-1 ) Arzu Simsek, Q. Luo, and A. Eder
Technical University Berlin, Germany
A new method based on the scan line method and a computer program for extracting parasitic effects from MCM mask layout data have been developed and are integrated in a design environment. This method and the design environment is presented. With this method the coupled lines and the discontinuities among N interconnection lines can be found.
4:00 p.m. 50,000 gate ASIC prototyping PLD using
Four Flex 8000 Devices and a Programmable Interconnect
(p10-2 ) Richard Terrill
Altera Corporation
As ASIC development cycles shrink, time-to-market become the overriding focus. Software simulations are slow and hence often cannot cover all expected states of the system. Multiple PLDS and a FPIC interconnect device were mounted on the same MCM substrate, to provide a small alternative to hardware emulation and to provide fast and efficient hardware verification of ASIC designs.
4:20 p.m. A Modular, High Performance, 2um
CCD-BiCMOS Process Technology for Application Specific Image Sensors
and Image Sensor Systems on a Chip
(p10-3) R.M. Guidash, P.P.K. Lee, J.M. Andrus, A.S. Cicarelli,
H.J. Erhardt, J. Fisher, E.J. Meisenzahl, P.H.Phil-brick,
and G. Ting
Eastman Kodak Company
This paper demonstrates the integration of high performance CCD, 2 um CMOS, and a vertical NPN in the same chip. This BiCMOS integration enable existing analog and digital current functions for application specific image sensors without perturbation of the CCD device characteristics.
Morris Chang, Chair
Rochester Institute of Technology
Subhash Roy, Co-Chair
TranSwitch Inc.
1:45 p.m. Session Introduction
1:50 p.m. Characterization of Opens in Logic Circuits
(p11-1) J. S. Rogenski, and F. Joel Ferguson
University of California at Santa Cruz
We present an algorithm for extracting opens in rectilinear circuit layouts using a plane-sweep technique. An implementation of the algorithm is used to characterize realistic opens in combinational circuit layouts. The occurrence of three types of opens possible in standard cells is examined. The number of single and multiple stuck-at faults due to opens in benchmark circuits is determined, assuming that floating nodes cause stuck-at faults. The distribution of open critical area between cells and routing, and between circuit layers is measured for the benchmark circuits.
2:10 p.m. An Analysis of Shorts in CMOS Standard Cell Circuits"
(p11-2) Alvin Jee
University of California, Santa Cruz
In order to provide high levels of IC quality, we must be able to detect the presence of a very high percentage of the defects that may occur in circuits. Our long term goal is to address this problem by developing guidelines to design circuits to be more easily tested without requiring complex fault models or testing techniques. This paper is a first step towards this goal. This paper contains data on which shorting defects are most likely to occur in CMOS standard cell circuits and which are most likely to not be detected by standard testing methods.
2:30 p.m. A Fault Coverage-Driven Partial Scan Chain
Selection Technique.
(p11-3) Clay Gloster
North Carolina State University
Partial scan, with it's low overhead, offers an alternative to the full scan design. The main problem in partial scan design is finding a minimal set of flip-flops to be included in the partial scan chain. In this paper, an algorithm for the selection of flip-flops to be included in the scan chain while providing 100% fault coverage is presented.
2:50 p.m. Dynamic Power Supply Current Monitoring of
SRAMs
(p11-4) Shyang-Tai Su, R. Z. Makki and H.T. Nagle
Hewlett-Packard
In this paper, the authors report the results of a physical experiment aimed at assessing a new test method for CMOS SRAMs. The test method involves monitoring the switching behavior of an SRAM circuit rather than just the output logic state. Observing the switching behavior of an SRAM can lead to drastic savings in test time. The authors use the dynamic power supply current as indicative of such switching.
Al Chiang, Chair
Brooktree Corporation
2:50 p.m. Session Introduction
2:55 p.m. Benchmarks Reveal Performance and Capacity
Tradeoffs of Programmable Logic Devices
(T12-1) Stephen Kliman
40 min. Altera Corp.
This tutorial discusses a standardized benchmark process for
comparing programmable logic devices. This talk presents benchmark
results from 35 devices using standards developed by the Programmable
Electronics Performance Corporation
(PREP). Capacity and performance
tradeoffs are shown for the different device architectures.
3:35 p.m. Synchronous Performance and Reliability
Improvement in Pipelined ASICs
(T12-2) Eby Friedman
60 min. University of Rochester
The clock frequency of a synchronous system can be increased by inserting registers within the data path (i.e., pipelining) thereby increasing the concurrent data flow of the system. The performance can be further increased by relocation of the registers so as to minimize the clock period while maintaining latency constant (i.e., retiming). Algorithms will be described for retiming pipelined systems. Extensions to these algorithms to handle electrical issues, such as clock distribution, register, and interconnect delays will also be discussed.
Clay Gloster, Chair
N. Carolina State University
Rafic Makki. Co-chair
University of N. Carolina
8:25 a.m. Session Introduction
8:30 a.m. Implementing a CMOS Boundry-Scan
Architecture Tutorial
(T13-1) Bibiche Geuskens, and K. Rose
40 min. Rensselaer Polytechnic Institute
This tutorial presents an overview of boundary scan and the IEEE 1149.1 Standard. The tutorial also discusses the VLSI implementation of boundary scan using the MOSIS SCMOS technology. As an example of such an implementation, the author reviews the results of two boundary scan test chips.
9:10 a.m. On Choosing the Right Error Models for Circuit
Testing
(T13-2) Robert Stave, D. Kao, and T.Y. Lin
40 min. University of California at San Diego
This tutorial presents an overview of error models which are used to correlate a fault model with the actual error patterns observed at the circuit's outputs. The presentation includes the following error models: The general, the Independent, and the Symmetric. The tutorial also provides general guidelines for choosing an appropriate error model for fault injection.
9:50 a.m. An Efficient Approach to Low Cost Sequential
Circuit Testing in BIST Environments.
(p13-1) Chien-In Chen, F. O'Bleness
Wright State University
This paper introduces a Built-In Self-Test Methodology with the goal of very high fault coverage for large VLSI circuits. The proposed methods, Circular Built-In Self-Test (CBIST) and CBIST with partial scan, are modeled after the principles of the Circular Self-Test Path. The simulation results include hardware overhead and improvement in fault coverage.
10:10-10:35 a.m. Break
10:40 a.m. Analog Built-In Self-Test
(p13-2 ) Mohammad S. Nejad, L. L. Sebaa, A. Ladick, H. Kuo
Western Digital Corporation, Irvine California
This paper presents approaches for on-chip measurement of passive components. Built-in test circuitry is used to measure external components. Built-in Self Test techniques for Digital to Analog converters (BIST-DAC) are also presented. Combined with boundary scan, these self-test techniques can be easily controlled.
11:00 a.m. Behavioral Fault Simulation and ATPG System
for VHDL
(p13-3) Tim H. Noh, C. Chen, and S.M. Chung
ELDC/Custom Microelectronics
This paper addresses the problem of fault simulation and ATPG using behavioral level circuit descriptions. The effectiveness of performing test generation for behavioral faults is evaluated by performing fault simulation on an equivalent gate-level representation of the circuit using test patterns generated by the behavioral ATPG system. Preliminary results show that the difference in fault coverage obtained from the behavioral and gate-level models is small for both combinational and sequential circuits.
11:20 a.m. An Efficient Tree-Based Algorithm for
Computing Path Delay Fault Coverage
(p13-4) Bhanu Kapoo and V.S. Sukumaran Nair
Texas Instruments Inc.
In this paper, a new algorithm for efficient computation of path delay fault coverage is presented. A directed acyclic graph (DAG) representing a combinational circuit is divided into a set of trees. An edge marking process based on path delay fault simulation over these trees provides a linear algorithm for computing path delay fault coverage.
11:40 a.m. A Study of Pipelined Pseudo-Exhaustive
Testing on VLSI Circuits with Feedback
(p13-5) Huoy-Yu Liou, T.Y. Lin, and C. Cheng
University of California at San Diego
In the process of embedding pipelined pseudo-exhaustive testing structures in complex designs, circuits under test are partitioned into clusters to reduce testing time for each cluster. To minimize test hardware, existing registers are utilized for pipelined signature propagation during the test mode. This paper presents results of a study on the impact of feedback loops in pipelined pseudo-exhaustive structures formed using existing registers.
Hyun Lee, Chair
AT&T Bell Labs
8:25 a.m. Session Introduction
8:30 a.m. Personal Appliance System and ASIC Architecture
(T14-1) Robert T. Franzo
90 min. AT&T
A case analysis of four different solutions for Personal Communicators/PDAs is presented in tutorial form. The tutorial also addresses the design considerations for a low-cost communication centric compute device and technology trends which will shape the future of this new class of devices.
10:00 a.m. FPGA Prototype Queuing Module for High
Performance ATM Switching
(p14-1) H. Duan, J.W. Lockwood, and S. M. Kang
University of Illinois at Urbana-Champaign
This paper describes a prototype Field Programmable Gate Array design that implements a queuing module for Asynchronous Transfer Mode switching. This queuing module achieves a bandwidth of 100 Mbps per switch port. The FPGA is used as an input queuing module of the point (Illinois Pulsar-based Optical Interconnect) tested.
10:10-10:35 a.m. Break
10:40 a.m. A Single Chip RSA Processor Implemented
in a 0.5mm Rule Gate Array
(p14-2) Shinji Ishll, K. Ohyama, and K.Yamanaka
NTT Corp.
A prototype single chip modular expotentiation has been implemented, which is capable of high-speed RSA public-key encryption processing. With this ASIC, computation can be done using the keys of arbitrary length up to 1024 bits. Throughput of 10kbps can be achieved. An ASIC of 105k gates was produced.
11:00 a.m. A Single Chip Multiprocessor DSP Solution for
Communication Applications
(p14-3) David Regenold
Intel Corporation
An architecture for a single chip multi-processor DSP solution for communication applications is presented. This integrated circuit was designed to handle the control, protocol, and data pump Functions necessary to implement high speed modem and audio tasks. The chip is based on multi-processor technology and consists of a 186 microcontroller with two Digital Signal Processing (DSP) co-processors.
11:20 a.m. A VLSI Processor Design of Real Time Data
Compression for High Resolution Imaging
Radar.
(p14-4) Wai-Chi Fang, P. Renick, M. Paller, and W. Johnson
Jet Propulsion Laboratory , Pasadena
An ASIC processor design has been developed to provide a real time data compressor for high resolution imaging radar systems. It explains the use of a Block Adaptive Quantizer (BAQ) algorithm. A compression ratio of 8:1, 8:2, or 8:4 at 30m piocels pre-season is achieved using one BAQ chip.
11:40 Four Channel DS1 Framer
(p14-5) Eugene L. Parrella and S.M. Chang
TranSwitch Corporation
An integrated circuit for framing on 4 independent TI lines has been developed. We discuss in detail the timing of the service and some of the approaches taken to move functions into RAM. We will also discuss novel approaches to TI alarm detection (AIS, LOS and Yellow) in the presence of a 1 in 10e-3 bit error rate. The chip's best features are also discussed.
Robert Inkol, Chair
DREO
Jim Kowalski, Co-Chair
Jet Propulsion Labs
8:25 a.m. Session Introduction
8:30 a.m. A Fast Logarithm Converter
(p15-1) Guenter Knittel
Universitaet Tuebingen, Germany
Many arithmetic operations are simplified when transformed to the logarithmic domain. This paper describes the design of a pipelined logarithm converter which is scaleable with respect to speed, precision, and chip area.
10:00 a.m. Pipelined 50 MHz CMOS ASIC for 32 Bit
Binary to Residue Conversion and Residue to Binary Conversion
(p15-2) Sathi Perumal and R. Siferd
Wright State University
VLSI implementations of a 32 bit binary to residue converter (BRC) and the corresponding residue to binary converter (RBC) are described. The pipelined inverted tree architecture used for both devices has been simulated to operate at clock rates exceeding 50 MHz for a 1 micron CMOS technology.
10:20 a.m. A 60 MHz ASIC B bit Serial/Parallel
Multiplier
(p15-3) Farook Moogat and R. Siferd
Wright State University
This paper presents a hardware implementation of a b-bit 16x16 serial/parallel multiplier based on the architecture of North and Ku. The circuit was designed to operate at a clock frequency of 60 MHz using complementary pass transistor logic implemented in 2 micron CMOS technology.
10:40 a.m. Design of a Processor Bus Interface ASIC for
the Stream Memory Controller
(p15-4) Sean McGee, J. Aylor, R.H. Klenke, and A. Schwab
University of Virginia
The Stream Memory Controller (SMC) is an experimental memory system that allows hardware-assisted memory access reordering for vector computations in order to maximize the efficiency of the system memory bus. The design was synthesized from a VHDL model.
11:00 a.m. A Low-Cost, Smart-Power BiCMOS Driver Chip
for Medium Power Applications
(p15-5) Goodwin Ting, R.M. Guidash, P.P.K. Kee and C. N.
Anagnostopoulos
Eastman Kodak Co., Rochester
This paper presents the development of a smart-power integrated driver circuit intended for low-cost, medium power switching and drive applications. The device contains, on one chip, CMOS digital control logic and bipolar drivers, with BiCMOS interface between the two technologies.
11:20 a.m. A High Performance SRAM-based FPGA
Device
(p15-6) Fred Slotnick, P. Butler, W. Li, D. Tang, and M. Shieh
Motorola Semiconductor Products
This paper demonstrates that previous performance objections to fine grained SRAM-based core-cell approaches to FPGA architectural design can be resolved. The performance and density obtained with the new architecture are compared to the corresponding results for more standard architectures.
11:40 a.m. Second Generation ORCA
Architecture Utilizing .5um Process Enhances the speed and User Gate
Capacity of FPGAs
(p15-7) Barry K. Britton, Yaw T. Oh, William Oswald,
Ho T. Nguyen, Satwant Singh, Chong Lee, Wai-Bor Leung,
Carolyn Spivak, Jim Steward and C. T. Chen
AT&T Bell Laboratories
This paper describes the second generation Optimized Reconfigurable Cell Array (ORCA) Field-Programmable Gate Arrays (FPGAs). Architectural innovations combined with advanced 0.5um process technology result in a family of high capacity and high speed FPGAs. New types of routing resources are included on the FPGA to ensure routing completion. The first ORCA part in the 2C series, the ATT2C15, contains approximately 2.5 million FETs and has a typical logic capability of about 15,000 usable gates. Preliminary benchmark results confirm the speed and logic capacity of the new parts.
Albicki, A., University of Rochester, NY
Ardalan, S., Pairie View A&M University, Prairie View, TX
Baker, S., Genesis Microchip Inc., Markham, Ontario, Canada
Barby, J., University of Waterloo, Ontario, CA
Boisvert, D.M., East Coast Labs, Salem, NH
Bowman, R., EDX, Fairport, NY
Braverman, D., NEC Electronics, Fairport, NY
Brown, G., Advanced Micro Devices, TX
Brown, G.A., Rochester Institute of Technology, NY
Chang, K.Y., Compass Design Automation, San Jose, CA
Chang, M., Rochester Institute of Technology, NY
Chen, H., IBM, Yorktown Heights, NY
Chen Chi, M., Industrial Technology Research Institute, Hsinshu, Taiwan
Chiang, A., Brooktree Inc., Boulder, CO
Childers, G., Intergraph Electronics, Boulder, CO
Chrusciel, R., ETEC, Inc., West Peabody, MA
Chung, S.S., National Chiao Tung University, Hsinchu, Taiwan
Cook, W., Eastman Kodak Company, Rochester, NY
Criado , A. R., ABB HAFO, Inc., San Diego, CA
Davis, A., Rochester Institute of Technology, NY
Deo, N., Philips Semiconductors, San Jose, CA
Eder, A., FH Augsburg, Augsburg,Germany
England, D., Intel Corporation, Chandler, AZ
Everts, J., Sandia National Laboratories, Albuquerque, NM
Fang, W, Jet Propulsion Laboratories, Pasadena, CA
Fertsch, M., Raytheon Microelectronics, Andover, MA
Gabara , T.J., AT&T Bell Laboratories, Allentown, PA
Gaboury, M., Fisher-Rosemount, Eden Prairie, MN
Gloster, C., North Carolina State University, Raleigh, NC
Greggain, L., Genesis Microchip, Inc., Markham, Ontario, Canada
Hayat, F., Cadence Design Systems, San Jose, CA
Honnenahalli, S., COMPASS Design Automation, San Jose, CA
Hsu, K.W., Rochester Institute of Technology, Rochester, NY
Hsu, Y., IBM, Yorktown Heights, NY
Hsu, Y, University of California at Riverside, Riverside, CA
Hull, R., Xerox Corporation, Webster, NY
Inkol, R. J., Department of National Defense, Ottawa, Ontario, Canada
Issa, S., Oki Semiconductor, Andover, MA
Kedem, G., Duke University, Durham, NC
Kim, C.B., Pacific Communication Science Inc., CA
Ko, U., Texas Instruments, Dallas, TX
Kowalski, J., Jet Propulsion Labs, Pasadena, CA
Lang, M., Xerox Corporation, Rochester, NY
Lee, H., AT&T Bell Labs
Lee,P.P.K., Eastman Kodak Company, Rochester, NY
Lefebvre, M., Carleton University, Ottawa, Canada
Lin, T.T., University of California, San Diego, CA
Lu, S.L., Oregon State University, Corgallis, OR
Makki, R., UNCC, Charlotte, NC
Mallinson, M., Crimble Micro Test, Inc., Billerica,MA
Meyer, D., IBM, Manassas, VA
Munoz, R. , Alcatel Network Systems, Raleigh, NC
Mukund, P.R., Rochester Institute of Technology, NY
Ong, D., Burr-Brown Corp. Tucson, AZ
Ostiguy, D.R., Texas Instruments, Waltham, MA
Paratore, B., Mobile Telesystems Inc, Gaithersburg, MD
Ramsay, F.R., Toshiba America Electronic Components, Sunnyvale, CA
Richards, W.R., MCNC, Research Triangle Park, NC
Robins, G., University of Virginia, Charlotte, VA
Roy, S , TranSwitch Inc., Shelton, CT
Ryan, C., University of Kentucky, Lexington, KY
Schrader, M., Eastman Kodak Company, Rochester, NY
Shastry, N.S., Toshiba Electronic Components, San Jose, CA
Smith, M.J., University of Hawaii, Honolulu, HI
Sridhar, R., SUNY at Buffalo, NY
Stroud, C., University of Kentucky, Lexington, KY
Thompson, D., AT&T Bell Laboratories, Allentown, PA
Traver, C., Union College, Schenectady, NY
Tsai, T., ITRI , Hsinchu, Taiwan
Van Iseghem, K.E., LSI Logic Corporation, Victor, NY
Xiong, X.M., Cadence Design Systems, Inc., San Diego, CA
Yung, Y., National Semiconductor, Santa Clara, CA
Technical Committee Photo(119K image file)
ABB HAFO, Inc.
Actel Corporation
Altera Corporation
Analogy, Inc.
AT&T Microelectronics
Beta Lambda
Cadence Design Systems
CLSI Solutions, Inc.
COMPASS Design Automation
Computer Design Magazine
Crimble Micro Test
DAZIX, An Intergraph Company
EM Associates
Fujitsu Microelectronics
Genesis Microchip, Inc.
GenRad, Ltd.
Hamilton/Avnet Electronics
Harris Corporation
Hewlett-Packard
Hitachi America Limited
i-LOGIX
IBM
IKOS Systems, Inc.
Intergraph Corporation
Integrated Measurement Systems
Mentor Graphics
Microelectronics Center of North Carolina
Mitsubishi Electronics
NCR
NEC
NeoCad
Quickturn Systems, Inc.
Racal-Redac
Raytheon Company
Silicon Systems, Inc.
S-Mos Systems
Steele, Stoltz & Associates
Sun Microsystems
Synopsys, Inc.
Tektronix, Inc.
Test System Strategies, Inc.
Texas Instruments
Top Down Design Solutions
Toshiba America
Vantage Analysis Systems
Viewlogic Systems, Inc.
VLSI Technology, Inc.
Zycad
