ASIC '95 Advance Program

Monday September 18

• 8:30 - 11:00
  • Registration
• 11:00 - 12:00
  • Keynote Session
• 12:00 - 1:30
  • Open Lunch
• 1:30 - 3:30
  • Paper Session 1 - Noise & Power
  • Paper Session 2 - Interconnects
  • Paper Session 3 - DSP Applications
• 3:30 - 5:30
  • Exhibitor Invites
• 5:30 - 7:30
  • Banquet Dinner
• 7:30 - 9:30
  • Panel Discussion

Tuesday September 19

• 8:30 - 12:00
  • Paper Session 4 - Circuits and Architecture
  • Paper Session 5 - Compression and Image Processing
  • Paper Session 6 - HDL Design Methodologies
  • Educational Tutorial - An Excursion Into VHDL
• 12:00 - 1:30
  • Luncheon
• 1:30 - 5:30
  • Paper Session 7 - Process, Reliability, & Packaging
  • Paper Session 8 - Simulation and Modeling
  • Paper Session 9 - Networking & Communication Applications
  • Educational Tutorial - VHDL Synthesis Techniques and Recommendations
• 5:30-6:30
  • Cocktail Reception
  Educational Tutorials are open to all conference attendees.

  Wednesday September 20

  • 8:30 - 12:00
    • Paper Session 10 - Analog and Mixed Signal
    • Paper Session 11 - Layout and Physical Design
    • Paper Session 12 - Test
    • Educational Tutorial - Solid-State Image Sensors (8:30-10:00)
    • Educational Tutorial - CCD Camera Design and ASIC Applications(10:30-12:00)
  • 12:00 - 1:30
    • Open Lunch
  • 1:30 - 3:30
    • Paper Session 13a - Analysis & Estimation
  • 3:30 - 5:30
    • Paper Session 13b - Novel Circuits
  • 1:30 - 5:30
    • Paper Session 14 Computing Applications
    • Paper Session 15 Synthesis and Module Compil ers
    • Educational Tutorial ATM Technology and Applications
  Educational Tutorials are open to all conference attendees.

  Thursday September 21

  • Full-day Workshops 8:30 - 5:30
    • AHDL Modeling for Analog and Mixed Signal Top-Down Design
    • From VHDL to CPLD - A Synthesizable Journey
    • Introduction to VLSI and ASIC Design Tools
  Workshops include lunch and require workshop registration.

  Friday September 22

  • Full-day Workshops 8:30 - 5:30
    • Low Power/Low Voltage Design and Technology
    • DSP IC Synthesis: Architectural Exploration with Mistral2
  • Half-day Workshops (8:30 - 12:00 or 1:30 - 5:30)
    • Practical Formal Verification of ASIC Designs
    • ASIC Test Synthesis: A Cost/Benefit Analysis
  Workshops include lunch and require workshop registration.