As technology scaling continues into deep submicron domain, interconnect parasitics has become dominant in determining chip performance and functionality. R(L)C delays becomes a significant portion of chip delay and noise/crosstalk caused due to parasitic coupling poses threat to circuit functionality. This tutorial covers several aspects of interconnect challenge - from process technology, parasitic extraction, R(L)C delay analysis, signal integrity and reliability analysis. The objective of the tutorial is to give the audience a broad perspective of the deep submicron challenges from academic and industrial perspectives and provide pointers to detailed information. The tutorial surveys the various academic and commercial solutions related to parasitic extraction and analysis. Academic and industrial results will be included to illustrate concepts and their significance.

Outline

Multi Level Interconnect Process Technology and Parasitic Modeling
Signal Integrity and Reliability Analysis