Behavioral Synthesis applies scheduling, allocation, resource sharing on a very high level of design abstraction. This sometimes makes the designers think far from the hardware resulting in less than acceptable Quality of Results(QoR) in terms of Timing and Area. Design Reuse is often used to take advantage of existing pieces of hardware to build a large system. Thus, both the behavioral synthesis and design reuse have the primary intention of higher productivity, even if it means sacrificing a marginal QoR. This presentation combines the advantages of behavioral synthesis and design reuse to enable the designers to think in terms of hardware even if designing at a behavioral level of abstraction to get the most out of hardware in terms of timing, area and possibly power in addition to productivity. This 4 hour Workshop is divided into 2 main sections: The first section describes the considerations in designing or reusing hardware that has the best possible timing and area. The second section presents the technique to encapsulate the above reusable hardware within a behavioral design to specify higher level requirements such as throughput and power. The workshop concludes with a behavioral design example applying reuse. I realize that with emerging Systems on a Chip (SoC) requirements, behavioral synthesis and design reuse are becoming indispensable.
 

Outline

Designing for Reuse Considerations

whether to reuse a partition as a hard macro or soft macro
whether or not it's meaningful to reuse a partition
Which techniques do I apply on each of the partitions before they are best reusable?

Adders
Multipliers
Operator Merging
Pipelining

Combinatorial Design Reuse
Pipelined Design Reuse
Specifying a Throughput
Design Example : Video Mixer