In this tutorial we examine noise as it affects ASIC designs and methods of achieving noise immunity. We start with a discussion of current and emerging deep submicron ASIC flows and the need for ensuring electrical correctness throughout the design to reduce costly iterations. An increasingly important component of electrical view is noise.

Current trends in technology such as smaller device dimensions, lower supply voltages, larger chip sizes, and  higher interconnect densities have contributed to making noise as an important criteria for designers as well as for tool developers.

Noise is generated through a number of sources including interconnect coupling, power supply distribution network, transistor leakage, as well as thermal noise, shot noise, flicker noise, and even alpha particles.

Noise causes timing failures such as setup and hold time violations, functional errors, and long term reliability problems.
We examine each type of noise and study their impact on DSM designs. Then we look at several methods for improving noise and evaluate their effectiveness. These methods include processing, packaging and design techniques, as well as
design optimization, physical planning and routing choices.

Then we see how these methods fit in ASIC design flows. The requirement for correct electrical view  leads us to noise modeling issues. Our focus here is on interconnect coupling as it affects timing performance and functional behavior of the design. We examine modeling requirements at different stages of the design.

Finally we discuss the requirements for standard noise formats. Such standards allow faster integration of "noise aware" tools and methodologies in the design flows.