Power consumption has become a significant design constraint, along with throughput, area, and accuracy, in VLSI systems.  This concern has been accelerated by the emergence of wireless systems, but exists even in high performance systems.  Next generation microprocessor designers forecast that future microprocessors could consume hundreds of watts per chip! In Systems on a Chip (SoC), in addition to the embedded processor core(s), the power budget includes the memory system (TLB, caches, eDRAM), I/O interfaces, on-chip system buses, and the subsystem communication interfaces (asynchronous contollers, local clock generators). Thus, power dissipation presents a number of design challenges in SoC's.  This tutorial will cover the techniques for lowering power consumption in SoC designs.

Outline

 Motivation - why worry about power
 Sources of power in CMOS circuits
 Overview of power analysis techniques/tools
 Gate level issues and techniques
 Function unit level issues and techniques

  Delay balancing
  Signal gating
  Guarded evaluation
  Precomputation
  Control state encoding

  Clock gating
  Sleep modes
  Clock power

  Clock generation/distribution
  Asynchronous alternatives

  Low power buses

   Signal encoding
   Low swing buses
   Segmented buses

  Low power memory systems

   TLBs
   Caches
   Embedded DRAMs

  Maintaining a constant supply voltage on-chip
  Sub-threshold (leakage) current concerns
  Power surges at power up and reset