This tutorial discusses challenges and solutions for high-performance interconnects geared at systems-on-chip. Technology scaling trends of deep-submicron multi-layer interconnects are analyzed, with special emphasis on their impact on systems-on-chip. Novel high-speed and low-power interconnect circuits and timing strategies are reviewed. The effects of on-chip inductance on interconnect performance are discussed. Interconnect optimization and CAD techniques that comprehend these inductive effects are studied.
 

Outline

Interconnect technology scaling challenges: RC degradation with scaling, low-K and Cu impact.
Towards better bus performance: timing strategies and circuit techniques for high-speed interconnects.
Inductance: impact in DSM technologies and how to handle them.
High-performance/low-power interconnect CAD: optimal tapering, repeater insertion, RLC optimization etc.