Dear Colleague ,
On behalf of the
Organizing and Technical Committees of ASIC '97, we invite you to attend
this year's conference in Portland, Oregon, U.S.A. For the last nine years,
this conference has been a forum for education and dissemination of new
ideas related to the ASIC community. We have an outstanding program to
offer you this year. Most technical sessions start with invited speakers
who are foremost experts in their respective technical areas. The tutorial
workshops have been carefully chosen to give you an opportunity to update
your skills. The papers are truly indicative of the work going on in many
countries. As such, we are sure that you will agree that ASIC '97 is an
outstanding event. Please use the registration
form for early registration.
| James Meindl,
Steering Committee Chair Georgia Institute of Technology |
P.R. Mukund,
General Chair Rochester Institute of Technology Phone: (716) 475-2174 e-mail: mukund@cs.rit.edu |
| Thaddeus
Gabara
Technical Program Chair Lucent Technologies Phone: (908) 582-2554 e-mail: gabara@physics.lucent.com |
Ramalingam Sridhar,
Technical Program chair SUNY at Buffalo Phone: (716) 645-2422 e-mail: rsridhar@eng.buffalo.edu |
| Keynote Speech: (Monday 9:00AM) | Invited Speakers: |
| Flash Memory-the Universal Digital Storage Medium for
the Coming Age of Consumer Electronics
by Dr. Eli Harari,
|
Anantha Chandrakasan, MIT
Mani Soma, University of Washington Dwight Hill, Synopsys Daniel Upp, Transwitch Corporation Robert Franzo, Lucent Technologies Robert Frye, Lucent Technologies David Allstot, Oregon State University James Armstrong, Virginia Tech. |
| Luncheon Speech:
(Tuesday 12:00PM)
Entrepreneurship in the U.S.
|
Banquet
Speech: (Monday 6:30PM)
The Future of EDA: An Alternative View 
Dr. John Tanner President & CEO, Tanner Research Inc. |
The conference will be held at the Portland Hilton, Portland, Oregon,
U.S.A. Indicate the group affiliation as "ASIC Conference" for special
rates of $125/night. Cut-off date for special rates is August 4, 1997.
The Hilton toll free number is 1-800-HILTONS and the URL is http://www.hilton.com/hotels/PDXPHHH/index.html.
You may also call the hotel directly at 503-226-1611.
8am-12noon and 1pm-5pm Full Day:
Visual HDL
by: Bob Hatt, Senior Applications Engineer, Summit Design,
Beaverton, OR
A one day workshop on using Graphical Entry/Debugging Tools from Summit Design Inc. to create VHDL simulation and synthesis models. In this hands on workshop users will create simulate and debug graphical description of VHDL models. A top down design approach using block diagrams, state diagrams, flowcharts, and truth tables as well as text HDL will be used to show the advantages of using graphical entry for design communication and debugging.
8am-12noon Half day:
ASIC Power Analysis Using QuickPower
by: Robert Kaye, Quickpower Tech. Marketing, Mentor Graphics
Corp., Wilsonville, OR
QuickPower is Mentor Graphics Power Analysis tool for
use in ASIC design flows. It plugs-in to the most popular digital simulators
in use in these design flows, and operates in a dynamic, interactive environment
with these simulators.
This half day workshop is designed to introduce the features
of QuickPower in the context of a QuickHDL based flow. It will explain
how QuickPower can be used to explore when & where power is being consumed
in a typical circuit. This analysis can be used to identify areas where
improvements in power consumption can be made.
The workshop assumes no previous knowledge of ASIC power
analysis tools. Basic understanding of the use of digital simulators will
be beneficial.
1pm-5pm Half day:
Synopsys' Synthesis
by: Dave Wilder, Staff Instructor, Synopsis Customer
Education, Synopsys, Inc., Sunnyvale, CA
This workshop is intended to give participants with no synthesis background a hands-on experience with Synopsys' synthesis methodology. The hands-on lab will be preceded by a presentation to familiarize the attendees with some key synthesis concepts. During the lab participants will be guided through a typical synthesis session, starting with Verilog or VHDL code, and resulting in a synthesized gate level netlist in a target ASIC technology. Participants will have the opportunity to explore the effects of coding style, partitioning and constraints on the resulting synthesized design. Participants are encouraged to also take the Synposis morning session "An Excursion Into VHDL."
8am-12noon Half day:
An Excursion Into VHDL
by: Joseph Pick, Staff Trainer Synopsis Customer Education,
Synopsys, Inc., Sunnyvale, CA
The IEEE standard hardware description language VHDL is
a prominent component of the design, documentation, and verification environment
of the electronics industry. This tutorial presents an innovative sequence
of tightly coupled VHDL models that introduce and develop the fundamental
principles of VHDL. Additionally, many advanced compilation and simulation
errors, based on real-world coding scenarios, are discussed and resolved
in full detail.
This tutorial presents a wide range of VHDL synthesis
coding styles and issues. Caveats based on real-world VHDL synthesis models
will be explored in full detail . Topics will be presented in the following
areas: VHDL synthesis fundamentals, importance of VHDL coding styles for
efficient hardware synthesis, simulation and synthesis mismatches, relying
on hardware design experiences, and behavioral synthesis.
1pm-5pm Half day:
Mixed Signal Scan Test - Past, Present, and Future
by: Keith Lofstrom, KLIC, Beaverton, OR
The IEEE 1149.1 boundary scan architecture tests purely
digital systems, but incompletely tests systems with analog and digital
signals mixed together. The proposed 1149.4 mixed signal test standard
adds analog test features to the existing standard.
The mixed signal scan test tutorial workshop will include
a brief overview of the existing 1149.1 standard, then cover in depth the
proposed 1149.4 standard and the implications for IC design. The tutorial
will briefly touch on future directions for mixed signal scan testing,
such as built-in signal generation and measurement, parametric wafer mapping,
and the testing of "difficult" components.
Monday, September 8, 1997
8:30 Opening Remarks: General Chair
8:40 Technical Program Overview: Program Chair
8:50 Invited Speakers: Program Chair
9:00 Keynote Speech: Dr. Eli Harari, President & CEO, SanDisk
Corporation
Flash Memory-the Universal Digital Storage Medium for the Coming
Age of Consumer Electronics
10:10 Exhibitors' Presentations
