Session 1 ASIC Applications

This session covers an array of technical challenges including small-area optical inputs in standard CMOS, magnetic field sensors, pixel cache, high resolution video, high speed multi-level combinational circuits, and space-saving ASIC packaging. The first paper is invited.

With the tremendous advances in process technology, ASIC integration capability has reached new levels that allow for developing complete systems on a chip, or System Level ASICs. However, just because silicon capabilities allow for these System Level ASICs, there are a number of other capabilities that are required to successfully implement these designs. One such capability is the use of macrocells functions to increase the level of integration. This paper discusses the challenges in designing macrocell functions to ease the ASIC integration process and some of the approaches used by the Microelectronics Group at Lucent Technologies (formerly AT & T Microelectronics) to overcome these challenges.

Small Area Optical Inputs for High-Speed CMOS Circuits
Farzad Esfahani, Karl-Otto Hofacker, Alexander Benedix, Horst H. Berger Technische Universitat Berlin, Germany
Compact and fast phonceivers with on-chip photodiodes have been developed as optical inputs for digital CMOS circuits. The performance of phtodiodes and current voltage converters has been investigated and optimized. The best performance with periodic signals of more than 250 MHz was found for a current comparator with statistically supplied reference photodiode

Stochastic Magnetic Field Micro-Sensor
Siegbert Hentschke IPM, Kassel University, Germany
This paper presents a new MAGFET-driven self-calibrating digital stochastic flip-flop micro-sensor for very small sensitive areas. Two types of digital MAGFET-cells have been designed: one for data detection and another for magnetic field magnitude measurement on a minimal area. The dynamic range is controlled by specialized feedback logic.

Maximizing Speed Performance of Multi-Level Combinational Circuits Implemented with Pass Transistors
Jose Luis Neves University of Rochester, Rochester, NY
Speed optimization techniques applied to combinational networks implemented with pass transistor gates are presented. The combination of optimization techniques and a set of pass transistor logic gates operate up to four times faster than the same circuit implemented with conventional logic gates.

Pixel Cache Architecture with FIFO Implemented within an ASIC
Tsuneo Ikedo The University of Aizu, Aizu-Wakamatsu, Japan
A graphics processor which uses a pipelined cache with FiFo to transfer in one cycle a three-dimensional pixel array and its Z values to the frame buffer is presented. A combination structure of cache and FiFO controlled by page mode in synchronous DRAM is effective to get enough bandwidth. A drawing speed of 4 million vectors per second (10 pixels/vector) or 1.2 million triangle polygons per second can be achieved.

Format Converter IC for Field Sequential Color Display
Wen-Hao Tsai Industrial Technology Research Institute, Hsinchu, Taiwan
A field sequential color display controller (FSCDC) was designed to format conversion of conventional video signals into field sequential format with a special frame memory design, a low-cost system can be implemented using conventional DRAMS. With a built-in 100 MHz DAC, FSCDC has been integrated using 0.8 um CMOS technology, occupying 30.4 mm².

Development of Embedded Card-type Processor, RICE25PC, and its Packaging Technology
Takeo Kikkawa NEC Corporation, Japan
Packaging, ASIC and PCB design techniques are combined to implement a credit card size processor for ATM switching systems. In this paper, the various techniques are described and evaluated.

Session 2 Architecture

Robert Landers, Chair
Texas Instruments, Dallas, TX
Cherrice Traver, Co-Chair
Union College, Schenectady, NY

Even as the semiconductor industry focuses on ever-lower-power system implementations, the expectation of improved performance in each generation of computing systems remains. Digital Signal Processing, in particular, is providing an impetus for this dual low-power, high performance thrust. Technology alone is no longer able to meet the increasing demand of such applications, either due to cost concerns or other limiting features of a given technology. the papers in this session describe solutions to these problems which supplement circuit-level performance enhancements with improvements in system architecture. The first paper in this session describes an architecture that significantly lowers the energy required to perform additions without unduly sacrificing performance. the nest paper presents a high performance full crossbar witch for use in Video Signal Processing systems. Paper three proposes a GaAs logic family with reduced static power, thereby giving the GaAs performance advantage to low-power systems which could not previously use this technology. The final paper shows a means of eliminating one of the roadblocks to the very-high-speed CMOS technique of wave-pipelining by allowing detection of delay faults in CMOS wave-pipelined circuits.

A compelling case is made for using MCM-D (thin film MultiChip Module) flip-chip technology to build a 'MegaChip' CPU consisting of an Instruction Fetch Unit and Execution Unit. By building part of the Instruction Fetch Unit in an optimized SRAM process, significant performance/cost gains are made. We also address the following important 'implementation' (1) Partitioning high speed paths across the chip boundary within timing specs; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; (4) Managing test costs; and (5) implementing a debug strategy. This paradigm is also potentially useful for other memory intensive applications, including ATM, etc.

A Fast Compact Addition Architecture for Low Power Microprocessors and DSP Chips
E.S. Gayles, R.M. Owens, M.J. Irwin The Pennsylvania State University, State College, PA
An addition scheme is presented which has comparable performance to carry-lookahead adders. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Our architecture is designed with a 3.3V 0.5(m process, and delivers the lowest-energy adders compared to other architectures.

High Performance GaAs Pseudo Dynamic Class of Logic
J.F. Lopez, R. Sarmiento, A. Nunez and K. Eshraghian Universidad de Las Palmas de Gran Canaria, Spain
Pseudo Dynamic Latched Logic (PDLL) is a new class of logic that derives benefits from both static and dynamic structures. Permanently refreshing circuitry allows functionality at low frequencies and high temperatures. A .86 GHz 4-b carry lookahead adder is implemented that is fully operational from 0( to 100( with power dissipation of only 5.2mW.

On-Line Detection of Environmentally-Induced Delay Faults in CMOS Wave Pipelined Circuits
R. Sridhar and A. Martinez-Smith State University of New York at Buffalo, Buffalo, NY
Circuits with CMOS wave pipelined logic gates are prone to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths, thus affecting the performance. Here, a delay fault sensing circuit is presented for CMOS wave-pipelining for on-line sensing. Its implementation for a wave-pipelined transmission gate logic cells is presented, with experimental results.

Session 3 Interconnect and Packaging

This session focuses on the increasingly important issues of parasitic R, L, and C in interconnect and packaging. The first paper extends the analytic delay for RC trees to ramp inputs while the second paper uses a hardware description language to model crosstalk between VLSI interconnect lines. The final paper develops an analytic delay expression of a CMOS output inverter which includes packaging parasitics.

Ramp Input Response of RC Tree Networks
Eby Friedman University of Rochester, Rochester, NY
An approach is presented for more accurately analyzing the delay characteristics of RC tree networks. The Penfield-Rubinstein-Horowitz approach to estimating the step function response of RC trees has been extended to ramp inputs. This improves timing accuracy by considering the shape of the input waveform driving each individual interconnect tree while maintaining computational simplicity for use in the automated timing analysis of complex VLSI circuits.

A Moment Matching Based Methodology for Crosstalk Analysis
Davide Pandini, C. Guardiani, C. Gubian SGS-Thomson Microelectronics, Italy
A new methodology for the crosstalk analysis of large VLSI IC interconnects finds a reduced order approximation of the original interconnect network using an extended moment matching technique. This model is implemented at behavioral level by a hardware description language.The effectiveness of the proposed method is demonstratedby application examples.

A Closed-Form Solution to the Damped RLC Circuit With Applications to CMOS Ground Bounce Estimation
Thaddeus Gabara Lucent Technologies, Murray Hills, NJ
A simplified RLC model can be used to determine the rise/fall time of a waveform. A closed form solution is developed to determine the rise/fall time of a buffer. The analysis was compared with the measurements of a 0.5umCMOS test chip with good results. Thus, the rise/fall time of a buffer is dependent on the values of the parasitic components in the system (R, L and C) and is not only a function of the buffer itself.

Session 4 Communications

This paper describes the challenges and trends in today's RF industry. Beginning with a brief look at the wireless communications environment, we examine receiver architectures and their building blocks from the point of view of monolithic integration. We then present trends in circuit and architecture design, device and technology development, and wireless infrastructures.

Design of Integrated RF Bandpass Filters zsnd Oscillators for Low-Power Radio Receivers
William Kuhn Kansas State University, Manhattan, KS
A CMOS LC oscillator operating at 200 MHz is reported, and a filter/oscillation theory that demonstrates the possibility of implementing a low power fully integrated pcs receiver for wideband service is presented.

A Flexible Direct Sequence Integrated Receiver with ARM Core
Bert Gyselinckx, M. Engels, Bolsens IMEC Belgium
A single-chip digital code division multiple access (CDMA) receiver ASIC is presented. The key feature of this chip is the integration of an ARM core on the ASIC and an entire direct-sequence spread-spectrum (DS SS) receiver with a maximum rate of 4x25Mc/s.

Differential PSK Detector ASIC Design for Direct Sequency Spread Spectrum Radio
Henrik Olson, D. Kerek, Oelmann, Tenhunen Royal Institute of Technology, Kista, Sweden
This paper presents an optimized architecture for differential PSK detection which effectively minimizes the logic complexity. This architecture has been implemented in a DS SS tranceiver circuit.

Low Complexity GSM Modulator for Integrated Circuit Implementations
Amit Bodas and Kamilo Feher University of California, Davis, CA
An IC design method of a reduced complexity for constant envelop modulation is presented. This design method is demonstrated on the globally standardized Graussian Minimum Shift Keying (GMSK) system.

An Integrated, Wireless Microinstrument for Monitoring Skin Temperature
Zaid Salman, S.H. Jones, R. M. Weikle, J. H. Aylor The University of Virginia, Charlottesville, VA
This paper describes the initial design and construction of an integrated wireless temperature microsensor designed to monitor skin temperature and transmit the information to a local receiver using a 350 MHz carrier frequency.

An ASIC for Transponder for Radio Frequency Identifcation System
Sau-Mou Wu, J.R. Yang, T. Liu Yuan-Ze Institute of Technology, Taiwan
This paper presents a novel and effective design of a self-powered (without battery) RFID transponder. It is compatible with the TIRIS, the popular RFID system by Texas Instruments. Data transmission uses FSK modulation

VLSI Design of the Reassembly Management for ATM/AAL
Kim-Joan Chen and C. L. Chang National Chung Cheng University, Taiwan
This paper presents a high memory efficient ATM/ALL reassembly management unit with a shared memory approach that employes the linked-list structure.

Simulation of a New Priority Control Method in VP-Based ATM Networks
Yu-Hyun Kim, C. Oh Electronics and Telecommunications, Taejon, Korea
This paper presents a new priority control method in up-based ATM networks that manages both system and network resource efficiently.

Single Chip DMT-Modem Transceiver for ADSL
Karel Adriaensen, Filip Van Beylen Alcatel Bell, Belgium
A complete digital processing of the Discrete Multitone modulation has been integrated into a single .5um CMOS device. The optimal power and area is achieved through algorithimc optimizations.

A GaAs ASIC Chip Set for 10 Gb/s SDH-based Optical Transmission System
Seog-hoon Lee, J. Kim, D. Kim Electronics and Telecommunications, Taejon, Korea
A GaAs gate array chip set has been designed for 10Gb/s SDH-based optical transmission system. Also a substantial decrease in operating frequency is achieved by implementing parallel STM-64 overhead functions.

Session 5 CAD

With the increasing acceptance of automation of the lower-level design tasks, designers are increasingly focusing their efforts at the more abstracts stages of the system-design process. In this paper, we examine some of the issues related to specification of embedded systems. We first introduce the notion of a conceptual model as being the first step of system specification. We demonstrate the need to have a one-to-one correspondence between the conceptual model and the specification language used to describe the system's functionality. We then present some of the salient characteristics of embedded systems. Finally, we evaluate the capabilities of several well-known hardware description languages - VHDL, Verilog, HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes)- with respect to specifying embedded systems.

Using Complex Sequential Modules in RTL Synthesis
Samit Chaudhuri and Michael Quayle Cadence Design Systems
A new RTL synthesis method capable of using complex sequential modules such as counters, accumulators and shift-registers is presented. This efficient mapping leads to smaller and more regular designs, and often better timing characteristics.

Architectural Exploration Using Behavioral Synthesis
Aruna Goli, Mike Lee, and Yu Chin Hsu University of California, Riverside, CA
Algorithms are presented for obtaining the design space of multiple communications processes. The performance of each process is analyzed and then combined to obtain the design space of the entire circuit. Experimental results for several designs are given.

Hardware Module Selection for Real Time Pipeline Architectures using Probabilistic Cost Estimation
O. Sentieys, J. Ph. Diguet, J. L. Philippe, and E. Martin Enssat-Lasti, France
This paper presents a new formalization and implementation of module selection for pipeline architectures under real time constraints. The cost function used is based on the area of selected components and a probabilistic estimation of the area of register, bus and interconnections. It includes some results in the real time digital signal processing field.

Performance Optimization and System Clock Determination for Synthesis of DSP Cores Targeting FPGAs
Shereef Shehata, B. Haroun, and A.J. Al-Khalili Concordia University, Montreal, Canada
An integer linear programming formulation for synthesis of high performance DSP architectures targeting FPGA implementations is discussed. The proposed approach explores a larger solution space and synthesizes more efficient and higher performance designs than previously possible with other approaches.

A New Approach for Boolean Function Minimization
T. Raju Damarla, Charles E. Stroud, and Gerald T. Michael National Resarch Council, Fort Monmouth, NJ
A new technique for representing and minimizing Boolean functions consisting of sum-of-products, XOR and XNOR is presented. This approach generates fewer product terms and results in a near optimal solution.

Use of Binary Decision Diagrams in the Modelling and Synthesis of Binary Multipliers
Kirk D. Lamb IBM Entwicklung Gmgh
This paper presents a method of partitioning the multiplier which restricts the complexity of the carry bits. This results in binary decision diagrams which grow no faster than the square of the number of inputs. The concept of largest possible BDD is also introduced.

Verification of ASIC Designs in VHDL Using Computer-Aided Reasoning
Edward Stabler, Michael Nassif, and Robert Paragi Syracuse University, Syracuse, NY
This paper describes a formal reasoning method for digital design verification. This method is applied to the verification of a 32-bit processor chip. The VHDL code for the processor has been proven to meet the formal specification.

Circuit Design Compliance Checking in VLSI Circuits
Kevin N. Lam and Stefan Rusu Compcore Multimedia, Inc., Santa Clara, CA
An electrical design rule analyzer for CMOS/BiCMOS transistor-level circuits is discussed. Rules for simple connectivity and sizing can be predefined to ensure acceptable circuit speed. VLSI circuits with over 3 million devices have been successfully verified by this method.

Performance-Driven Layer Assignment for Printed Circuit Boards and Integrated Circuits
C.J. Richard Shi, A. Vannelli, and J. Vlach University of Iowa, Iowa City, Iowa
This paper considers how to assign wire segments into two layers so as to minimize the number of vias, while taking into account performance constraints such as layer preference and circuit timing. We propose two solution methods using integer linear programming and an extension of a network partitioning heuristic. Experimental results are included.

Multichip Module Placement with Heat Consideration
Man Chak Tang and Jo Dale Carothers The University of Arizona, Tucson, AZ
An algorithm for multichip module placement using a combined quad-partitioning, genetic search and simulated annealing approach is presented. In addition to minimizing wire length and vias, the algorithm places chips so that heat is evenly distributed over the substrate. Results are compared with those from the simulated annealing and min-cut algorithms on the MCC benchmarks.

MCM Multilayer Routing with Layer Balancing
Jo Dale Carothers, Tingyang Liu, and Donghui Li The University of Arizona, Tucson, AZ
We describe an innovative layer balancing algorithm, to enhance the multichip module/dense PCB router, MCG. The layer balancing algorithm can evenly distribute nets as well as total wirelength and vias among multiple layers without increasing the number of layers. The results of testing on the standard MCM benchmarks as well as the routing results for JPL's pathfinder decoder board are presented.

A Unified Placement Algorithm to Improve Both Performance and Area through Sliceable Partitions
Carsten Recke and Alfred Eder Technical University of Berlin, Germany
A new placement approach is presented integrating the legal placement arrangement into a combined method of global placement and constrained partitioning for simultaneous optimization of performance and area aspects based on slicing enumeration. Computation times of the algorithm for practical problems are proven to be of practical use.

Design of a Multichip Module Containing a 12Way S/390 Microprocessor Subsystem
Helmut Kohler IBM Entwicklun GmbH, Germany
This paper presents the development strategy of a high performance S/390 CMOS microprocessor subsystem packaged on a 127mm MCM. The MCM houses the complete processor core components like PU, FPU, L1-cache, L2-cache, Bus-switch and DMA-controller. The MCM-internal-net count was above 10,000 while the signals leaving the MCM passed 1700. Chip size is up to 14.5mm x 14.5mm.

Session 6 Simulation and Modeling

This session addresses simulation and modeling at various levels of the hierarchy beginning at the system level and ending at the gate level utilizing a top down approach. The session opens with a paper describing a system simulation tool which predicts future performance, power, and area limits for high performance ASICs. Paper two suggests a solution for selecting and evaluating functional simulation vectors. Paper three estimates power and timing for a deep sub-micron CMOS inverter driving an RC load. The final paper presents a method to equalize the high-to-low and low-to-high propagation delays of a CMOS inverter with different input slew rates, load capacitance, and NMOS transistor width.

A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001
John Eble, Vivek De, D. Wills, J. Meindl Georgia Institute of Technology, Atlanta, GA
GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a road map for interconnect design, and performance, energy, and area limits.

Sampling Based Design Verification Using Design Error Models
Sungho Kang Yonsei University, Seoul, Korea
A new simulation based design verification system,based on design error models, provides a simulation coverage estimate using statistical sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient design verification tool to reduce the overall design cycle time.

Timing and Power Models for CMOS Repeaters Driving Resistive Interconnect
Eby Friedman and Victor Adler University of Rochester, Rochester, NY
A delay and power model of a CMOS repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS repeaters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time and for short-circuit power dissipation for aCMOS repeater driving a resistive-capacitive interconnect line.

An Analytical Approach to Fine Tuning in CMOS Wave-pipelining
R. Sridhar and S. Talukdar The State University of New York at Buffalo
Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay.

Session 7 Digital Signal Processing

Digital Signal Processing is the enabling technology for wireless computing, indispensable for RF signal processing, as well as providing the compute horsepower for compression of image and sound information to fit the available bandwidth. The papers in this session have caught the wave of wireless computing, with two papers on DSP techniques for radio receivers, and two papers covering the spectrum of image compression. Our final paper covers speech recognition which is the opportunity for wireless communication between human and machine.

Recently, much press has been given to DSP implementations in programmable logic, often on the strength of a few simple benchmarks. This paper will examine more complicated DSP systems design in programmable logic, starting with an analysis of the support models required from the device vendors, and the new tools that will be needed. A set of examples, from simple to complex, that have been designed with initial versions of the tools called for in this paper will be presented. Finally, some methods for achieving high performance designs in programmable logic will be described.

New Architecture for High Throughput-Rate Real-Time 2-D DCT and the VLSI Design
Jen-Shiun Chaing and H.C. Huang Tamkang University, Taipei, Taiwan
A new architecture for a 2 dimensional Discrete Cosine Transform has been developed, featuring: 1) a programmable logic array (PLA) replaces multipliers, 2) pipelining and overlapped row-column operations speed operations, 3) highly modular and regular structure. The architecture implements a 8x8 2-D DCT at 50 MHz (800 macs/sec) in a .8 micron spdm CMOS process.

Design of an ASIC Architecture for High Speed Fractal Image Compression
Alessandro DeGloria, F. Ancarnai, Oliveieri, and Stossone University of Genoa - DIBE, Italy
The design and performance of an ASIC dedicated to fractal image compression has been synthesized from VHDL and hosted on a PC platform via the PCI bus. The hardware performance is 300 times the performance of the algorithm running on a 100 MHz Pentium system. Implementation requires 150,000 transistors.

Micro Pipeline DSP-ASIC for a DS-SS Receiver
Bengt Oelmann and Hannu Tenhunen Royal Institute of Technology, Kista, Sweden
A fully asynchronous DSP circuit for a Direct-Sequence Spread Spectrum radio receiver. Issues in micropipeline VLSI implementation and performance are discussed. The design uses a .8 micron CMOS standard cell with 100,000 transistors. The receiver handles up to 48 million samples per second and the power consumption is 600 mw.

Real-Time Implementation os Speech Recognition using RISC Processor Core
Chung-Tze Chang, H.L. Yang, H.T. Chang and
C.T. Chang Industrial Technology Research Institute, Hsinchu, Taiwan
A general purpose Risc based processor with analog support has been implemented for Speech Recognition applications. The system is designed for large vocabulary, integrates speech analysis, feature extraction and pattern recognition, achieving high performance at low cost.

A 400 Megasample Per Second Digital Receiver ASIC
Robert Inkol, Valek Szwarc and M. Esonu Defence Research Estqablishment, Ottawa, Canada
An ASIC has been designed for digital quadrature demodulation and other signal processing functions in electronic warfare receivers. It directly accepts digitized IF data from a separate 8 bit A/D. The use of a fully pipelined, parallel architecture in GaAs gate array allows nominal sampling at 400 MHz, allows for a -3db bandwidth exceeding 80 Mhz.

High-Performance Crossbar Interconnect for a VLIW Video Signal Processor
A. Wolfe,S. Dutta, K. J. O'Conner Princeton University, Princeton, NJ
A high-performance crossbar interconnect designed in a 0.25 (m process for a VLIW Video Signal Processor (VSP) chip is presented. Novel optimizations and design choices are presented that are unique to single-chip-processor crossbars. Area and speed tradeoffs are examined for a variety of design parameters to guide architectural decisions for the VSP.

Session 8 Test

This session starts with an invited paper from Vishwani D. Agrawal of Lucent Technology. Next, work on analog behavioral fault modeling using hardware description language is presented. Third, a new technique for weighted random pattern generation is given. The fourth paper presents circuit partitioning techniques for distributed VHDL fault simulation. The fifth paper presents results on error bit identification of signature. Next, a technique for path-delay fault simulation for mixed level circuits is presented. Finally, a parallel test generation technique based on boolean satisfiability is given.

Wide differences in test signals used for analog and digital circuits make a common test for a mixed-signal device difficult. A divide and conquer strategy partitions the circuit into three types of blocks: analog, digital logic and memory. A design for testability structure using boundary scan and analog test bus allows very effective test application. With this design, separate specialized tests are applied to analog and digital parts, as well as to interconnects. While the partitioned architecture provides a reasonable test solution, weakness remains in the test of block interfaces. Research on unified analog-digital tests is recommended. Delay tests and current measurement tests might be possible candidates.

Behavioral Fault Modeling and Simulation of Phase-Locked Loops Using a VHDL-A Like Language
C.J. Richard Shi and N. Godambe University of Iowa, Iowa City, Iowa
A new methodology called induced behavioral fault modeling is presented for fault simulation and testing of analog and mixed-signal circuits. This methodology is to use layout and process defect information to derive a set of transistor level faults. These faults are modeled and simulated with behavioral hardware description language. This offers better modeling and faster simulation as compared to traditional techniques.

An Alternative View on Weighted Random Pattern Testing
Arno Kunzmann and Ralf Seepold Forschungszentrum Informatik, Karlsruhe, Germany
This paper describes an approach for weighted random test pattern generation based on the computation of global weights. The method uses a partly specified deterministic test pattern set and an estimation of the required random pattern length. By stimulating some primary inputs with inverted weights, the test length can be minimized. The results show a very high fault coverage, short random pattern length, and low hardware costs.

Circuit Partitioning for Distributed VHDL Fault Simulation
Chirstopher Ryan Texas Instruments, Stafford, TX
This paper addresses the problem of long simulation time for switch-level fault simulation by using a novel switch-level circuit partitioning technique with distributed simulation. Transistor reverse level order circuit partitioning is shown to produce increased speed-up over distributed switch-level fault simulation using random fault set partitioning techniques.

Efficient Error Bit Identification from Failing Signature
Charles Stroud and T. Raju Damarla Univesity of Kentucky, Lexington, KY
The paper presents an efficient idenification of bit errors in the input to single and multiple input signature registers by using characteristic polynomial constructed from the product of multiple polynomials. The identifcation algorithm used is based on look-up tables with a total number of entries equal the sum of the orders of the polynomials.

An Efficient Path-Delay Fault Simulator for Mixed Level Circuits
Sungho Kang, Y.T. Yim, S. Kang Yonsei University, Seoul, Korea
This paper describes a path fault simulator and introduces a new algorithm using new logic values. The new simulator can consider mixed level circuits that can treat delay faults more closely to their elecrical behavior.

A Parallel Test Generation for Combinational Circuits Based on Boolean Satisfiabiltiy
Yuzhong Sun and Daozheng Wei Chinese Academy of Sciences, Beijing, China
A parallel algebraic algorithm to implement ATPG for combinational circuits on a distributed computing environment is presented. This algorithm employs a "path-oriented expanded implication graph" (POEIG) as a heuristics guide to improve the stochastic calculation of Boolean satisfiability formula of a circuit.

Session 9 Mixed Signal/Analog

The Analog/Mixed Signal Session has 3 selected and 1 invited paper covering a broad range of current topics in the field. The session starts with an invited talk. The second paper describes a high speed CMOS comparator aimed at LAN transciever applications. The circuit designed in a 0.9 um process, using a 5 volt supply, can achieve 0.7 mV resolution at a 60 MHz sampling rate. The third paper, a CMOS crystal oscillator, is targeted for wireless applications. Using 10-bit binary weighted capacitor arrays, the oscillation frequency is digitally trimmable to an accuracy of 0.3 ppm. The phase noise is -100dBc/Hz at 100 Hz offset. The fourth paper describes a low power digital phase lock loop. It is used for frequency multiplication and for advanced power management both at the device level and at a system level. The last paper in the session uses module-based design approach to synthesise a multi-port two-dimensional filter. A library of switched current (SI) cells is used in the implementation of the filter.

Adaptation and learning are key elements in biological and artificial neural systems for computational tasks of perception, classification, association, and control. They also provide an effective means to compensate for imprecisions in highly efficient analog VLSI implementations of parallel application-specific processors, which offer real-time operation and low power dissipation. The effectiveness of embedded learning and adaptive functions in analog VLSI relies on careful design of the implemented adaptive algorithms, and on adequate means for local and long-term analog memory storage of the adapted parameter coefficients. We address issues of technology, algorithms, and architecture in analog VLSI adaptation and learning, and illustrate those with examples of prototyped ASIC processors.

A 60 MHz 0.7 mV Resolution CMOS Comparator
Zhilong Tang and Douglas Frey AT&T Bell Lab
A CMOS comparator consisting of two pipelined regenerative amplifiers is described. The comparator, designed for high-speed data communication, achieves 0.7 mV at 60 MHz rate in 0.9 um CMOS.

A 800 uA, 105 MHz, CMOS Crystal-Oscillator Digitally Trimmable to 0.3 PPM
Philipp Basedau and Qiuting Huang Swiss Federal Institute of Technology
An 105 MHz crystal oscillator uses banks of binary weighted capacitors to digitally trim the oscillation frequency to 0.3 ppm. The measured results include -100 dBC/Hz phase noise at 100 Hz offset at 1.7 V.

SI Technique Application for Color Image Processing
Andrzej Handkiewicz, P.Sniatala, M.Domanski, and M. Lukowiak Poznan University of Technology
A synthesis method is developed to design a multi-port two dimensional filter. This method incorporates a library of switched current subcells using module-based design tools.

Low Power Digital PLL
Rafael Fried, EPFL Swiss Federal Institute of Technology
A low power Digital Phase Lock Loop (DPLL) is presented. It is used for frequency multiplication and for advanced power management both at the device level and at a system level.

Session 10 Low Power Design

This session is dedicated to the subject of Low Power circuit design, techniques, and methodologies. Clustered Voltage Scaling is compared to gate re-sizing in the second paper. Spice models and simulations are used to reduce power in low voltage flash memories in the third paper. The fourth paper outlines a number of methods to reduce power in a 2D DCT. This session ends with a presentation that highlights methods that minimize power in static CMOS datapaths.

Recent advances in adiabatic or non-dissipative computation, as reflected in conceptions of novel static and dynamic energy recovery logic families, are described. The energy, power and peak power of these logic families are compared with conventional static and dynamic CMOS. Key challenges to successful implementation of adiabatic systems are summarized.

Low Power Design Technique for ASICs by Partially Reducing Supply Voltage
Kimiyoski Usami, Takashi Ishikawa, Kanazawa, Kotani Toshiba Corporation, Kawasaki, Japan
Comparison of two techniques of power reduction: Clustered Voltage Scaling (CVS) and Gate Sizing. The CVS technique reduces supply voltage partially thus providing power reduction without performance degradation. Results indicate better power reduction with CVS than with gate resizing.

Reducing Power Dissipation in Low Voltage Flash Memories
Brenda Luderman Motorola, Austin, TX
A new low voltage flash circuit model is presented. Spice Models identify techniques for reducing the average power. Simulations are discussed that show results.

Low Power Design of Two-dimensional DCT
Shih-Lien Lu and Jim Li Oregon State University, Corvallis, OR
Several techniques for reducing power in 2D-DCT's (Discrete Cosine Transforms) are described. These techniques include removal of circuit blocks of insignificance, re-ordering of operations to reduce transition probability and re-designing cells for low voltage.

Optimal Circuit Design for Low Power CMOS GSI
Azeez Bhavnagarwala , Vivek De, D. Austin, and J. Meindl Georgia Institute of Technology, Atlanta, GA
Presentation of methodologies that minimize total power drain of datapaths in static CMOS systems without loss of performance through optimal device, circuit and system design. Spice simulations verify operation over different operating ranges.

Thursday 8:00 am- 12 noon
1 RF Design
Steve Maas, Nonlinear Technologies

The RF Design Basics tutorial workshop will cover receivers (design of LNAs, mixers, IF/baseband, and RF detection); transmitters (PA design, power control, and I/Q modulators); frequency synthesis (VCO design, PLL design); related topics (DC bias techniques, S parameters, Smith charts, etc). Technologies considered will be Si BJT and CMOS.

Thursday 8:00am - 12:00 noon
2 The IEEE Standard VHDL Synthesis Packages
J. Bhasker, Bell Laboratories

In this tutorial workshop, we will provide a look at the two standard VHDL synthesis packages that are (or will soon be) an IEEE standard. The tutorial will explain in-depth the types and the various subprograms that make up the two packages. The two packages, NUMERIC_BIT and NUMERIC_STD, are arithmetic packages directed specifically for providing portability of VHDL synthesis models. The package NUMERIC_BIT contains arithmetic operations based on the type BIT, while the package NUMERIC_STD contains arithmetic operations based onthe type STD_LOGIC. The rationale behind the design of the packages will also be presented. This tutorial workshop will also provide practical application usage of the packages in synthesizable VHDL models. This will demonstrate the portability feature of models that use these synthesis packages. Examples such as counters, finite-state-machines that use these packages will also be shown.

Thursday 1:30pm - 5:30pm
3 Algorithms and Standards for Wireless Communications
Brian Woerner, Virginia Tech

This tutorial workshop introduces the audience to the various aspects for wireless algorithms. The main algorithms used in today's wireless applications will be introduced. Data compression algorithms and error correction techniques are some of the topics that will be covered.An overview of this tutorial and a biography of the presenter is available here.

Thursday 1:00 pm - 5:30 pm
4 Design and Implementation of Advanced Digital Wireless Communication Systems
Ravi Subramanian, Synopsys, Inc.

This tutorial workshop provides an overview of paging, messaging, cellular, and cordless systems; an examination of the key signal processing issues trend and implication analysis for the portable communications market. Design techniques covered include: modeling transceivers, homodyne, heterodyne, IF sampling, phase-detectors, simulations, DSP techniques, synchronization, and equalization. Various architectures will be explored, for both hardware and software. A number of ASIC solutions using DSP/uPs will be presented as well. The COSSAP tool set will be used to demonstrate the design, implementation, and verifications steps along the way. An outline of this tutorial is available here.

Friday 8:00 am- 12 noon
5 Low-Power Design
Kaushik Roy, Purdue University
Rabinda Roy, NEC

This tutorial on low-power design aims at educating the audience about the recent advances in the following areas: Design for low-power at various levels of design abstraction; Architectural level techniques for low-power; Software issues related to low-power design; Supply voltage scaling versus design performance; Power estimation techniques; Testability of low power circuits; and Future trends in low-power design such as adiabatic computing and SOI technology.

Friday 8:00 am- 12:00 noon
6 Programmable DSP Architectures for VLSI System Solutions
Arup Gupta, Bell Labs

In the first part of the tutorial, programmable DSP architectures from major vendors will be presented. Key architectural and performance differences between the architectures will be discussed. The tutorial will begin with the first generation products, and then get into the lead and derivative products of the second generation.Finally technology and architectural trends of third generation embedded DSP processors will be discussed. An outline of this tutorial and a biography of the presenter is available here.