Authors:
Norman Rohrer is a Senior Technical Staff Member in the PowerPC Microprocessor Group within the Microelectronics Division of IBM located in Essex Junction, VT. Norman received his Bachelor's Degree in physics and mathematics from Manchester College, North Manchester, IN in 1987. He received his Master's Degree and Doctor of Philosophy degree in electrical engineering from The Ohio State University, Columbus, OH in 1990 and 1992, respectively. Norman holds 3 patents and is co-author, along with Kerry, on two books titled High Speed CMOS Circuit Design Styles and SOI Circuit Design Concepts.
Kerry Bernstein is a senior technical staff member and lead technologist in the High Speed Server Processor Business Group at IBM Microelectronic Division's Essex Junction, Vermont facility. He is currently responsible for future product technology definition, performance and application. Mr. Bernstein received the B.S degree in electrical engineering degree from Washington University in St.Louis, and joined IBM in 1978. He holds 25 US Patents, and is has co-authored 3 college textbooks and multiple papers on high speed CMOS. His interests are in the areas of low power and high speed electronics. Mr. Bernstein is a senior member of the Institute of Electrical and Electronic Engineers, and is on the International Solid State Circuits Conference Program Committee. He serves as an industrial mentor for the Semiconductor Research Corporation, and is on the staff of "Neurosurgery Update" at the Marine Biological Laboratory, Woods Hole, MA.

Authors:
Dr. Lei He obtained the Ph.D. degree in computer science from UCLA, and joined the faculty of ECE dept., University of Wisconsin at Madison in 1999. His research focuses on design and design automation of high-performance and power-efficient circuits and systems, and have worked extensively on interconnect modeling and optimization. He was the primary developer of TRIO package, a tool set for interconnect synthesis, including routing construction, buffer insertion, device sizing, wire sizing, and wire spacing. He worked with HP Laboratories in 1998 summer and fall, and proposed the inductance extraction methodology used in state-of-the-art microprocessor designs at HP.
Dr. Shen Lin got his Ph.D from the EECS department of UC, Berkeley in 1992. He joined IBM T.J. Watson Research Center. from 1992-1995, and LSI Logic from 1995-1997. Since 1997, he has been with HP Labs working on design methodology, signal integrity, inductance, power/ground optimization, and clock skew minimization. He held one US patent on low power circuit design technique, filed four US patent applications, and published numerous technical papers.

Authors:
Fabrice Paillet received the M.S. degree in Electrical Engineering in 1996 from Paris XI University, FRANCE. He is currently working toward the Ph.D. degree at the Geography Imagery and Perception laboratory in Arcueil, FRANCE. He owns two patents. His present interests are in VLSI/Computer Architecture, Low Power and particularly Integrated Programmable Computational Image Sensors Design.
Damien Mercier graduated from Ecole Polytechnique in 1993, and obtained an M.S. degree in electronics from Paris XI University in 1995. After five years at GIP labs, where he became the leader of the PAR project, he is now director of the computer department at ENSTA, Paris. His main research interests are smart sensors and computer architecture.

Authors:
Mircea R. Stan received the Diploma in Electronics from the Polytechnic Institute of Bucharest, Romania, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst. Since 1996 he has been an assistant professor in the Electrical Engineering Department and the coordinator of the High-Performance Low-Power (HPLP) lab at the University of Virginia. Dr. Stan is teaching and doing research in the areas of low-power VLSI, mixed-mode analog and digital circuits, computer arithmetic, and embedded systems. Dr. Stan has more than eight years of industrial experience with companies in Romania, Japan and the US. In 1997 Dr. Stan received the NSF CAREER Award for investigating low-power design techniques. He is a member of IEEE, ACM, Usenix and also of Phi Kappa Phi and Sigma Xi.
C.K. Ken Yang graduated with B.S, M.S., and Ph.D. at Stanford University in 1992, 1993, and 1998 respectively. He joined Rambus Inc. during a leave of absence for one year to design a 500MB/s memory interface on a 16Mb DRAM. His Ph.D. dissertation focussed on the design of high-speed serial links in CMOS technology. After completing his dissertation research on a 4-6Gb/s serial link, he jointly supervised several other links-related projects on a 14-b 10MS/s DAC, an 8-Gb/s multi-level equalized transceiver, and a 10-GS/s 4-bit ADC. He joined UCLA in January of 1999. His research interests are in the area of high-performance digital and mixed-signal circuit design. Current research areas include the design of high-speed data and clock-recovery circuits for large digital systems (6-10Gb/s), design of low-power, high-performance functional blocks, clock distribution for high-speed digital processing, and low-power high-precision capacitive sensing interface design for MEMS applications.

Abstract:
The workshop will address the use of 1149.4 as a substrate for Analog Test support within a mixed signal circuit. While 1149.4 is primarily used to access the internal analog components from an external test machine, this workshop will outline how the same on-chip components that are needed to support 1149.4 may be used internally by an Analog Built In Self Test (ABIST) system.

Author:
Martin Mallinson is the CTO of Silicon Analog Systems, fabless semiconductor design center based in British Columbia. Martin has over 20 years experience in mixed signal circuit IC design and holds many patents in this area. Martin founded Crimble Micro Test Inc. in 1992 and with his team of engineers designed the first hardware reprogrammable mixed signal IC test machine.

Authors:
Dr. Steven McCormick, is Vice President of Engineering at Sapphire Design Automation. He was most recently manager of the delay calculation group at Cadence Design Systems. While at Cadence, he oversaw the development of key technologies required to accurately calculate timing for deep submicron design. From 1989 to 1993, he worked at DEC's SEG heading up the effort to develop signal integrity analysis tools.
Andrew B. Kahng is professor and vice-chair of the UCLA computer science department. He was the founding General Chair of the 1997 ACM/IEEE International Symposium on Physical Design, and is active in the MARCO Gigascale Silicon Research Center as well as the SIA ITRS effort. His research interests include VLSI physical layout design and performance analysis, combinatorial and graph algorithms, and stochastic global optimization.
Dr. Sudhakar Muddu is Senior Member of Technical Staff with SGI's microprocessor group. He has also worked at Intel Corporation in Santa Clara, IBM T. J. Watson Research Center in Yorktown Heights, and AT&T Bell Laboratories in Holmdel. He has also worked for MIPS Technologies in microprocessor design and integration groups. His research interests include Computer-aided-design of VLSI circuits, Architecture design and Computer Network modeling and analysis.