THURSDAY, SEPTEMBER 14 - MORNING
TA1: IP CORE DESIGN
Regency Ballroom A
Session Chair: John Chickanosky, IBM
Session Co-Chair: Thomas Büchner, IBM
8:15 a.m.
TA1.1
Invited paper: Cultivating the Disciplines of Reusable IP Development : ASIC Cores Methodology Initiatives, C. Ashley, E. Keller, O. Strohacker, D. Reed, IBM Microelectronics, Essex Junction, VT
8:40 a.m.
TA1.2
Parametrizable Hybrid Stack-Register Processor as Soft Intellectual Property Module, T. Roewer, P. Luethi, M. Stadler, D. Forrer, and S. Moscibroda, Integrated Systems Laboratory, Zurich, Switzerland
9:05 a.m.
TA1.3
HiPAR-DSP - A Scalable Family of High Performance DSP-Cores, J.P. Wittenburg, W. Hinrichs, H. Lieske, H. Kloos, L. Friebe, and P. Pirsch, University of Hannover, Hannover, Germany
9:30 a.m.
TA1.4
Improved VLSI Designs for Multiplication and Inversion in GF(2M) over Normal Bases, L. Gao and G.E. Sobelman, University of Minnesota, Minneapolis, MN
TA2: CIRCUIT DESIGN AND MIXED SIGNALS
Regency Ballroom B
Session Chair: P R Mukund, Rochester Institute of Technology
Session Co-Chair: Paul Lee, Eastman Kodak
8:15 a.m.
TA2.1
Direct-Conversion Quadrature-Modulator for 0.8-1 GHz with Flip-Chip Passives, E. Tiiliharju, A. Friman and K. Halonen, Helsinki University of Technology, Helsinki, Finland
8:40 a.m.
TA2.2
Optimization of A 0.13um CMOS Backend Interconnect Process for ASIC SOC: Low k Dielectric vs Cu Conductor, P. Bendix, W. Loh, J.J. Lee, and W. Li, LSI Logic, Milpitas, CA
9:05 a.m.
TA2.3
An Efficient Method for Estimating Switching Activity in Arithmetic Circuits Using a Lumped Delay Model, R. Sridhar, SUNY Buffalo, Buffalo, NY
9:30 a.m.
TA2.4
Blind Estimation and Error Correction in a CMOS ADC, J. Elbornsson, Linköping University, Linköping, Sweden
9:55 a.m.
Break
THURSDAY, SEPTEMBER 14 - MORNING (continued)
TA3: IP DESIGN METHODOLOGY
Regency Ballroom A
Session Chair: Dave Braverman, NEC
Session Co-Chair: John Chickanosky, IBM
10:20 a.m.
TA3.1
IVE : An Internet Based distributed VHDL Environment, K. Yang, A. Windisch*, T. Schneider, J. Mades, M. Glesner, and W. Ecke**, Darmstadt University of Technology, Darmstadt, Germany, *Technical University of Chemnitz, Chemnitz, Germany, and **Infineon Technologies, Munich, Germany
10:45 a.m.
TA3.2
Low Level Watermarking of VLSI Designs for Intellectual Property Protection, D.L. Irby, R.D. Newbould, J.D. Carothers, J.J. Rodriguez, and W.T. Holman, University of Arizona, Tucson, AZ
TA5: MODELING AND REUSE
Regency Ballroom A
Session Chair:
Session Co-Chair:
11:10 a.m.
TA5.1
Designing Reusable Components in VHDL, M. Chang and K. Agun, Illinois Institute of Technology, Chicago, IL
11:35 a.m.
TA5.2
A Layered Approach to Behavioral Modeling of Bus Protocols, S. Chonnad and B. Needamangalam, Synopsis, Inc., Mountain View, CA
TA4: CODESIGN: CASE STUDIES ANDMETHODOLOGIES
Regency Ballroom B
Session Chair:
Session Co-Chair:
10:20 a.m.
TA4.1
Robust Mobile Computing - A Case Study in Architecture Performance Evaluation, R. Kress and S. Schulz*, Infineon Technologies, Munich, Germany and *University of Arizona, Tucson, AZ
10:45 a.m.
TA4.2
SOC-Driven Design Methodology for Full Custom High Performance Mixed-Signal Designs, R. Wittmann, W. Schardein*, D. Bierbaum, and M. Darianian, Nokia Research Center, Bochum, Germany and *University of Applied Sciences, Dortmund, Germany
11:10 a.m.
TA4.3
Coware Pipelining for Exploiting Intellectual Properties and Software Codes in Processor-based Design, H. Choi and I.-C. Park*, Samsung Electronics, Seoul, Korea and *KAIST, Seoul, Korea
11:35 a.m.
TA4.4
Architecture Level Optimization for Asynchronous IPs, W. Hardt, M. Visarius and B. Kleinjohann*, University of Paderborn, Paderborn, Germany and *C-LAB: Cooperative Computing & Communications Laboratory, Paderborn, Germany
12:00 p.m.
Luncheon with Guest Speaker: James Urquhart, Chief Operating Officer, ARM Holdings
THURSDAY, SEPTEMBER 14 - AFTERNOON
TP1: MODELING AND REUSE
Regency Ballroom A
Session Chair:
Session Co-Chair:
1:30 p.m.
TP1.1
Analysis of VHDL Semantics through a High-Level Synthesis Tool, G. Savaton, E. Casseau and E. Martin, UBS University, Lorient, France
1:55 p.m.
TP1.2
Design, Optimization, and Implementation of a Universal FFT Processor, P. Kumhom, J.R. Johnson and P. Nagvajara, Drexel University, Philadelphia, PA
2:20 p.m.
TP1.3
Methodology and Code Reuse in the Verification of Telecommunication SOCs, O. Petlin, A. Genusov and L. Wakeman*, ASIC-Alliance Corporation, Woburn, MA and *Lucent Technologies, Holmdel, NJ
2:45 p.m.
TP1.4
Development and Application of a Macro Model for Flash EEPROM Design, M. O'Shea, A. Concannon, K. McCarthy, B. Lane, A. Mathewson, and M. Slotboom*, National Microelectronics Research Centre, Cork, Ireland and *Philips Research Laboratories, Eindhoven, The Netherlands
TP2: APPLICATIONS I
Regency Ballroom B
Session Chair: Thomas Büchner, IBM
Session Co-Chair: Dave Braverman, NEC
1:30 p.m.
TP2.1
Design of Front-end Processor Core for Max. 64X-Speed CD-ROM Drive System, A. Wada, T. Otsuka, K. Tani, and T. Sawai, Sanyo Electric Co., Ltd., Gifu, Japan
1:55 p.m.
TP2.2
An Embedded PowerPC™ SOC for Test and Measurement Applications, B. Blaner, D. Czenkusch*, R. Devins, and S. Stever*, IBM Microelectronics, Essex Junction, VT and *Agilent Technologies, Loveland, CO
2:20 p.m.
TP2.3
A Mixed-Mode Single-Chip Motor-Drive-Specific Microcontroller with a 12-bit 125KS/s ADC, J.-C. Kim, S.-H. Lee, J.-Y. Kim, Y.-C. Jang, I.-S. Mok* and H.-J. Park, Postech, Pohang, Korea and *Research Institute of Industrial Science and Technology, Pohang, Korea
2:45 p.m.
TP2.4
A 64/256 QAM Receiver Chip for High-speed Communications, D. Shin, K.H. Park and M.H. Sunwoo, Ajou University, Suwon, Korea
3:10 p.m.
Coffee Break
THURSDAY, SEPTEMBER 14 - AFTERNOON (continued)
TP3: BUILDING BLOCKS
Regency Ballroom A
Session Chair: Mike Gaboury, Rosemount Inc.
Session Co-Chair: David England, Intel
3:35 p.m.
TP3.1
An Energy-Efficient Leakage-Tolerant Dynamic Circuit Technique, L. Wang, R.K. Krishnamurthy*, K. Soumyanath, and N.R. Shanbhag, University of Illinois, Urbana, IL and *Intel Corp., Hillsboro, OR
4:00 p.m.
TP3.2
A Program Compression Technique Supporting IP-centric SOC Design, C. Yeh and C.-S. Wang, National Chung Cheng University, Chia-Yi, Taiwan, ROC
4:25 p.m.
TP3.3
Low-Power 4-Way Associative Cache for Embedded SOC Design, H. Choi, M.-K. Yim, J.-Y. Lee, B.-W. Yun, and Y.-T. Lee, Samsung Electronics, Seoul, Korea
4:50 p.m.
TP3.4
Digit-Serial Fixed Coefficient Complex Number Multiplier-Accumulator on FPGAs, T. Sansaloni, J. Valls, and K. Parhi*, University Politecnica de Valencia, Valencia, Spain and *University of Minnesota, Minneapolis, MN
TP4: APPLICATIONS II
Regency Ballroom B
Session Chair: Thomas Büchner, IBM
Session Co-Chair: Dave Braverman, NEC
3:35 p.m.
TP4.1
Low Power Video Object Motion Tracking Architecture, W. Badawy and M. Bayoumi, RA, Lafayette, LA
4:00 p.m.
TP4.2
Design Self-Synchronized Clock Distribution Networks in an SoC ASIC using DLL with Remote Clock Feedback, H.Q. Nguyen, H. Lee and D.W. Potter, Lucent Technologies, Allentown, PA
4:25 p.m.
TP4.3
Using Computational RAM for Volume Rendering, A. Snip, D. Elliott, M. Margala, and N. Durdle, University of Alberta, Edmonton, Alberta, Canada
4:50 p.m.
TP4.4
ICORE: A Low-Power Application Specific Instruction Set Processor for DVB-T Acquisition and Tracking, T. Gloekler, S. Bitterlich and H. Meyr, Aachen University of Technology, Aachen, Germany
5:50 p.m.
7:00 p.m.
Transportation to Dinner Cruise
Banquet - Dinner Cruise
 |
 |
 |
 |
 |
 |
