FRIDAY, SEPTEMBER 15 - MORNING
FA1: LOW POWER: MODELS, ARCHITECTURE AND TOOLS
Washington Room A
Session Chair: Katsu Nakamura, Analog Devices
Session Co-Chair: Mike Gaboury, Rosemount Inc.
8:15 a.m.
FA1.1
Modeling Energy of the Clock Generation and Distribution Circuitry, D. Duarte, M.J. Irwin and V. Narayanan, Pennsylvania State University, University Park, PA
8:40 a.m.
FA1.2
Orthogonal Partitioning and Gated Clock Architecture for Low Power Realization of FSMs, R. Shelar, H. Narayanan* and M.P. Desai, Silicon Automation Systems, Bombay, India and *Indian Institute of Technology, Bombay, India
9:05 a.m.
FA1.3
A Complete Model for Glitch Analysis in Logic Circuits, K.-S. Chung, T. Kim* and C. L. Liu**, Synopsis, Inc., Mountain View, CA, * KAIST, Taejon, Korea and **National Tsing Hua University, Hsinchu, Taiwan, ROC
9:30 a.m.
FA1.4
POPS: A Tool for Delay/Power Performance Optimization, N. Azemard, M. Aline and D. Auvergne, LIRMM-University of Montpellier, Montpellier, France
FA2: PHYSICAL DESIGN TECHNIQUES
Washington Room B
Session Chair:
Session Co-Chair:
8:15 a.m.
FA2.1
Design of a Databus Charge Recovery Mechanism, V. Narayanan, V. Lyuboslavsky, B. Bishop, and M.J. Irwin, Pennsylvania State University, University Park, PA
8:40 a.m.
FA2.2
On-Chip Decoupling Capacitor Optimization using Architectural level Current Signature Prediction, M. Pant, P. Pant and D.S. Wills, Georgia Institute of Technology, Atlanta, GA
9:05 a.m.
FA2.3
Design of Low-Capacitance Bond Pad for High-Frequency I/O Applications in CMOS Integrated Circuits, M.-D. Ker, H.-C. Jiang* and C.-Y. Chang, National Chiao-Tung University, Hsinchu, Taiwan, ROC and *ITRI, Hsinchu, Taiwan, ROC
9:30 a.m.
FA2.4
High Level Estimation of the Area and Power Consumption of On-Chip Interconnects, D. Langen, A. Brinkmann and U. Rückert, Heinz Nixdorf Institute, Paderborn, Germany
9:55 a.m.
Break
FRIDAY, SEPTEMBER 15 - MORNING (continued)
FA3: LOW POWER CIRCUITS
Washington Room A
Session Chair:
Session Co-Chair:
10:20 a.m.
FA3.1
Power Optimization of Delay Constrained Circuits, A. Nayak, M, Haldar, P. Banerjee, C. Chen, and M. Sarrafzadeh, Northwestern University, Evanston, IL
10:45 a.m.
FA3.2
Low-Power Skewed Static Logic (S2L) with Topology-dependent Dual Vt, C. Kim, J. Lee, K.-H. Baek, and Sung-Mo Kang, University of Illinois, Urbana,IL
11:10 a.m.
FA3.3
Power Optimization of Standard Cell Flip Flops, B. Rasmussen and J.A. Wright, American Microsystems, Inc., Pocatello, ID
FA5: FORMAL METHODS
Washington Room A
Session Chair:
Session Co-Chair:
11:35 a.m.
FA5.1
Model Reductions in MDG-based Model Checking, J. Hou and E. Cerny, Université de Montréal, Montréal, Québec, Canada
12:00 p.m.
FA5.2
Formal Representation of Gated Clock Designs, T. Seceleanu and J. Plosila*, Turku Center for Computer Science, Turku, Finland and University of Turku, Turku, Finland
FA4: SIGNAL INTEGRITY
Washington Room B
Session Chair:
Session Co-Chair:
10:20 a.m.
FA4.1
Characterization of Interconnect Coupling Noise using In-Situ Delay-Change Curve Measurements, T. Sato, Y. Cao*, D. Sylvester**, and C. Hu, Hitachi, Ltd., Tokyo, Japan, *University of California, Berkeley, CA and **Synopsys, inc., Mountain View, CA
10:45 a.m.
FA4.2
A Differential High-Speed Digital CMOS Buffer with Hysteresis for Improved Noise Immunity, R. Secaraenu and E.G. Friedman, University of Rochester, Rochester, NY
11:10 a.m.
FA4.3
Capturing Input Switching Dependency In Crosstalk Noise Modeling, L. Chen, M. Marek-Sadowska, R. Divecha, and P. Singh, University of California, Santa Barbara, CA
11:35 a.m.
FA4.4
Efficient Static Timing Analysis in Presence of Crosstalk, T. Xiao, C.-W. Chang and M. Marek-Sadowska, University of California, Santa Barbara, CA
12:00 p.m.
FA4.5
An Effective Modeling Technique for the Delay Calculation and the Skew Analysis for Clock Grid Designs, G. Kim, D.-S. Cho and J.-T. Kong, Samsung Electronics Co., Ltd. Yongin-City, Korea
12:15 p.m.
Open Lunch
FRIDAY, SEPTEMBER 15 - AFTERNOON
FP1: HIGH PERFORMANCE AND LOW POWER
Washington Room A
Session Chair:
Session Co-Chair:
1:30 p.m.
FP1.1
Dynamic-Threshold CMOS SRAM Cells for Fast, Portable Applications, A. Bhavnagarwala, A. Kapoor and J.D. Meindl, Georgia Institute of Technology, Atlanta, GA
1:55 p.m.
FP1.2
An Zero-Overhead Self-timed Divider using New Pipeline Scheme, J.-L. Yang, C.-S. Choy and C.-F. Chan, The Chinese University of Hong Kong; new Territory, Hong Kong
2:20 p.m.
FP1.3
Scalable Binary Sorting Architecture Based on Rank Ordering With Linear Area-Time Complexity, I. Hatirnaz and Y. Leblebici, Worcester Polytechnic Institute, Worcester, MA
2:45 p.m.
FP1.4
High Throughput FIR Filter Design for Low Power SoC Applications, A.T. Erdogan and T. Arslan, University of Edinburgh, Edinburgh, United Kingdom
3:10 p.m.
FP1.5
Low Power Controller Optimization Based on Data Path Pattern Extraction, P.-Q. Zou and C.-Y. Tsui, Hong Kong University of Science and Technology, Hong Kong
FP2: SYNTHESIS AND BACK END TOOLS
Washington Room B
Session Chair:
Session Co-Chair:
1:30 p.m.
FP2.1
Right Topologizer: An Efficient Schematic Generator for Multi-level Optimization, N.-H. Kim, K.-S. Kim, K.-M. Choi, and J.-T. Kong, Samsung Electronics, Yongin City, Korea
1:55 p.m.
FP2.2
Predictable Routing, R. Kastner, E. Bozorgzadeh and M. Sarrafzadeh, Northwestern University, Evanston, IL
2:20 p.m.
FP2.3
Real Time Application Architectural Synthesis Dedicated to Sub-Micron Technologies, E. Casseau and J. Martin, UBS University, Lorient, France
2:45 p.m.
FP2.4
Cell Library Development using Multi-Objective Function Optimization, M. Delaurenti, M. Graziano, G. Masera, G. Piccinini, and M. Zamboni, Politecnico di Torino, Torino, Italy
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